From 0f2ef422e36d53ba7dd6d31ac949ad55d44490e1 Mon Sep 17 00:00:00 2001 From: dylanbenzi Date: Sun, 27 Sep 2026 18:05:49 -0400 Subject: [PATCH] remove scaffolding comments --- testplan_initial.md | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/testplan_initial.md b/testplan_initial.md index 325bf30..db7fd8a 100644 --- a/testplan_initial.md +++ b/testplan_initial.md @@ -97,7 +97,6 @@ small area to debug. ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADD), .rd(2), .rs1(1), .rs2(2)), @@ -131,7 +130,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(1), .imm(1)), EBREAK_WORD @@ -164,7 +162,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(1)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(1), .imm(-1)), EBREAK_WORD @@ -197,7 +194,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(0x123)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(0x123)), asm_instr(.op(OP_ADD), .rd(2), .rs1(1), .rs2(2)), @@ -231,7 +227,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(0x123)), EBREAK_WORD }; @@ -263,7 +258,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), EBREAK_WORD }; @@ -295,7 +289,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(1)), asm_instr(.op(OP_SUB), .rd(1), .rs1(0), .rs2(1)), EBREAK_WORD @@ -328,7 +321,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(0x123)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(0x23)), asm_instr(.op(OP_SUB), .rd(2), .rs1(1), .rs2(2)), @@ -362,7 +354,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(32)), asm_instr(.op(OP_SRL), .rd(1), .rs1(1), .rs2(2)), @@ -396,7 +387,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(32)), asm_instr(.op(OP_SLL), .rd(1), .rs1(1), .rs2(2)), @@ -430,7 +420,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_SLL), .rd(1), .rs1(1), .rs2(0)), EBREAK_WORD @@ -463,7 +452,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_SRL), .rd(1), .rs1(1), .rs2(0)), EBREAK_WORD @@ -496,7 +484,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(1)), asm_instr(.op(OP_SLL), .rd(1), .rs1(1), .rs2(2)), @@ -530,7 +517,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(1)), asm_instr(.op(OP_SRL), .rd(1), .rs1(1), .rs2(2)), @@ -564,7 +550,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(4)), asm_instr(.op(OP_SLL), .rd(1), .rs1(1), .rs2(2)), @@ -598,7 +583,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(4)), asm_instr(.op(OP_SRL), .rd(1), .rs1(1), .rs2(2)), @@ -632,7 +616,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_LW), .rd(1), .rs1(0), .imm(0)), EBREAK_WORD }; @@ -664,7 +647,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_SW), .rs1(0), .rs2(1), .imm(0)), EBREAK_WORD @@ -697,7 +679,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_LW), .rd(1), .rs1(0), .imm(4)), EBREAK_WORD }; @@ -729,7 +710,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_SW), .rs1(0), .rs2(1), .imm(4)), EBREAK_WORD @@ -762,7 +742,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_LW), .rd(1), .rs1(0), .imm(-1)), EBREAK_WORD }; @@ -794,7 +773,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_SW), .rs1(0), .rs2(1), .imm(-1)), EBREAK_WORD @@ -827,7 +805,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_LW), .rd(0), .rs1(0), .imm(0)), EBREAK_WORD }; @@ -859,7 +836,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_BEQ), .rs1(0), .rs2(0), .imm(8)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(1)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(2)), @@ -893,7 +869,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_BEQ), .rs1(0), .rs2(1), .imm(8)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(-1)), @@ -927,7 +902,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)), asm_instr(.op(OP_ADDI), .rd(2), .rs1(0), .imm(-1)), asm_instr(.op(OP_BEQ), .rs1(1), .rs2(2), .imm(8)), @@ -963,7 +937,6 @@ prog = '{ ```systemverilog prog = '{ - // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)), EBREAK_WORD, asm_instr(.op(OP_ADDI), .rd(1), .rs1(0), .imm(-1)) }; @@ -1020,7 +993,6 @@ biases and why the resulting programs remain useful and terminating. **Implementation outline:** ```systemverilog -// Write the intended loop and lifecycle using seqr.gen_program(...). int min_len = 2; int max_len = 50; int random_progs = 50;