Initial snapshot from fall_26_member
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Ethan Huang
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# Fall 2026 DV Onboarding Test Plan
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<!--
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Make two copies of this template:
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1. testplan_initial.md, submitted before implementing tests.
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2. testplan_final.md, updated after implementation and coverage closure.
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Keep the initial copy unchanged after review. HTML comments are editing
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instructions and disappear from rendered Markdown.
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-->
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## NOTE: THIS IS A TEMPLATE FOR YOU TO FOLLOW. THIS IS **NOT** A COMPREHENSIVE TESTPLAN. YOU NEED TO EXTEND IT.
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## Document information
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| Field | Value |
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| --- | --- |
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| Verification engineer | Name, Discord username, GT username |
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| Plan revision | Initial / Final |
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| Date | YYYY-MM-DD |
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### Revision history
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| Revision | Date | Changes |
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| --- | --- | --- |
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| Initial | YYYY-MM-DD | Initial planned tests |
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| Final | YYYY-MM-DD | <!-- Tests or constraints added after debugging and coverage review --> |
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## 1. Functional tests
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<!--
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Plan tests for the CPU functionality supported by this onboarding. Organize
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related behavior together. Include both individual instruction behavior and
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multi-instruction sequences where ordering or dependencies matter.
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Add as many rows and detailed test records as needed. Do not put every CPU
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operation into one large program: each failure should identify a reasonably
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small area to debug.
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-->
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### Functional-test summary
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| Test ID | Test name | Functionality being tested | Expected result | Status |
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| --- | --- | --- | --- | --- |
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| 1.1 | `test_name` | | | Planned |
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| 1.2 | | | | Planned |
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| 1.3 | | | | Planned |
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### Functional-test details
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<!-- Duplicate this complete record for every functional test. -->
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### 1.1 — `test_name`
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**Functionality:** <!-- State exactly what CPU behavior this test checks. -->
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**Initial state:**
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- Registers: <!-- Usually reset state unless the program establishes another value. -->
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- Data memory: <!-- List relevant initialized word addresses and values, or write “none.” -->
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- Other setup: <!-- Reset, program timeout, number of words to read back, etc. -->
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**Program:**
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<!-- Use the same representation that will be placed in run_member_directed_tests(). -->
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```systemverilog
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prog = '{
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// asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)),
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EBREAK_WORD
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};
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```
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**Expected result:**
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| Register or memory word | Expected value | Calculation or explanation |
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| --- | --- | --- |
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| `x__` | `32'h________` | |
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| `dmem[__]` | `32'h________` | |
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**Pass criteria:** <!-- Include halt/timeout behavior and any state that must remain unchanged. -->
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**Final result:** <!-- Complete in testplan_final.md: pass/fail and useful log or waveform reference. -->
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## 2. Constrained-random tests
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### Instruction constraints
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<!--
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Explain the provided constraints, then record how the partial and open
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constraints are completed. State what each constraint permits, excludes, or
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biases and why the resulting programs remain useful and terminating.
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-->
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| Constraint | Provided, partial, or open | Behavior and purpose | Final implementation summary |
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| --- | --- | --- | --- |
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| `c_opcode` | Provided | | No member change |
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| `c_reg_bias` | Provided | | No member change |
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| `c_imm_range` | Partial | | |
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| `c_mem_align` | Open | | |
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| `c_imm_unused` | Provided | | No member change |
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| `c_branch_target` | Partial | | |
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| `c_no_branch_at_end` | Provided | | No member change |
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| `c_branch_taken_bias` | Open | | |
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### External-port constraints
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| Constraint | Provided, partial, or open | Behavior and purpose | Final implementation summary |
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| --- | --- | --- | --- |
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| `c_align` | Provided | | No member change |
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| `c_valid_window` | Partial | | |
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| `c_reg_read_only` | Provided | | No member change |
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| `c_data_corners` | Open | | |
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### Random-program test
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| Item | Plan |
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| --- | --- |
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| Number of programs per seed | |
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| Program-length range | |
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| Information logged for reproduction | Numeric `SVSEED`, iteration, and complete generated program |
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**Implementation outline:**
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```systemverilog
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// Write the intended loop and lifecycle using seqr.gen_program(...).
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```
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## 3. Assertions
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<!--
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Plan at least two assertions in addition to the supplied example. Write the
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timing rule in English first. In the final plan, include the exact SVA and
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evidence from a temporary violation proving that the assertion can fire.
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-->
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### Assertion summary
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| Assertion ID/name | Behavior checked | When it is sampled/disabled | Activating test |
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| --- | --- | --- | --- |
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| 4.1 / `PROPERTY_NAME` | | | |
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| 4.2 / `PROPERTY_NAME` | | | |
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### 4.1 — `PROPERTY_NAME`
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**Timing requirement in words:**
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```systemverilog
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PROPERTY_NAME:
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assert property (@(posedge clk) disable iff (rst)
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/* property expression */)
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else assertion_fail("descriptive failure message");
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```
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**Evidence that it detects a violation:** <!-- Temporary change, failing log/waveform, and confirmation after reverting it. -->
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### 4.2 — `PROPERTY_NAME`
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**Timing requirement in words:**
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```systemverilog
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PROPERTY_NAME:
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assert property (@(posedge clk) disable iff (rst)
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/* property expression */)
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else assertion_fail("descriptive failure message");
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```
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**Evidence that it detects a violation:**
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## 4. Encrypted CPU Bug Hunt
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### Random discovery
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| Field | Evidence |
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| ------------------------ | ----------------------------- |
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| Discovery command | `make bug_hunt SEED=random` |
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| Numeric `SVSEED` | |
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| Failing iteration | |
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| First failure message | |
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| Reproduction command | `make bug_hunt SEED=________` |
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| Reproduces consistently? | Yes / No |
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**Original failing program:**
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```systemverilog
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prog = '{
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// Paste original generated sequence
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EBREAK_WORD
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};
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```
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### Expected vs. actual
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| Instruction / event | Expected | Actual | Cycle/time |
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| ------------------- | -------- | ------ | ---------- |
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| | | | |
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**First architectural divergence:**
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<!-- State the first register, memory, or control-flow result that becomes incorrect. -->
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### Minimization
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**Minimized reproducer:**
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```systemverilog
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prog = '{
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// Smallest sequence that still fails
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EBREAK_WORD
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};
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```
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### Waveform evidence
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Include a screenshot showing the offending instruction and the first incorrect architectural result.
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### Conclusion
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**Trigger:**
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<!-- Smallest condition that causes the failure. -->
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**Expected behavior:**
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<!-- ISA-correct behavior. -->
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**Observed behavior:**
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<!-- What the encrypted CPU does instead. -->
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**Behavioral characterization:**
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<!-- One precise sentence. Do not speculate about hidden RTL. -->
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