Initial snapshot from fall_26_member
This commit is contained in:
Ethan Huang
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# Design Verification Onboarding — Fall 2026
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## Subteam overview
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### Description
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The Design Verification (DV) subteam checks that a design behaves according to its specification
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before it is manufactured. DV members work with RTL designers to identify functionality, write test plans,
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build simulation environments, find failures, and report enough evidence for a designer to
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reproduce and fix each bug.
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This onboarding introduces that thought process using the CPU from the Digital Design onboarding.
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You are not being asked to build another CPU or a testbench framework from scratch. The routine
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class, mailbox, assembly-helper, waveform, and watchdog infrastructure is provided so you can focus
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on deciding:
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- what behavior needs to be tested,
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- how to drive it without creating races,
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- what must be observed independently,
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- how to predict the correct result,
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- how to recognize a failure, and
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- how to show that the verification plan is complete.
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> This testbench does **not** use UVM. Its sequencer, driver, monitor, scoreboard, and coverage
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> components use the same separation of responsibilities found in larger UVM environments.
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### Tools used
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- Cadence Xcelium (`xrun`) for compilation and simulation
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- Cadence SimVision for waveform debugging
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- Cadence IMC for RTL code coverage
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- SystemVerilog classes, mailboxes, constraints, assertions, and coverage reports
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## Onboarding project
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After you add your CPU RTL, the supplied verification scaffold compiles but is intentionally
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incomplete.
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Submit the first version of your test plan during the first week, before implementing its test cases. The plan is a working engineering document: revise it whenever coverage or debugging exposes missing behavior.
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The final stage runs the same completed testbench against an encrypted CPU containing multiple
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injected bugs. Finishing the onboarding means both demonstrating that your own CPU passes and using
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constrained-random stimulus to find and characterize all three encrypted failures.
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## Chip-level verification contract
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You already learned the CPU datapath and supported instructions during Digital Design onboarding.
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This section covers the external behavior that this testbench must drive and observe.
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### External address map
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The external port is byte addressed and accepts word-aligned accesses. `addr_i[13:12]` selects a
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window:
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| `addr_i[13:12]` | Window | Base | Size | Access |
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| --- | --- | --- | --- | --- |
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| `2'b00` | Instruction SRAM | `0x0000` | 1024 words | read/write |
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| `2'b01` | Data SRAM | `0x1000` | 1024 words | read/write |
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| `2'b10` | Register file | `0x2000` | 32 words | read only |
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| `2'b11` | Unmapped | — | — | none |
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Word `n` is located at `base + n*4`.
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### External-port protocol
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- A write presents `addr_i`, `wdata_i`, and `w_en_i`; the request is captured at the next rising
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edge.
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- A read holds `addr_i` and `r_en_i` until `rready_o` is observed. SRAM windows respond on the
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following cycle; the register-file window responds in the request cycle.
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- `w_en_i` and `r_en_i` must never be asserted together.
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- The external port is serviced only while the CPU is disabled.
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- Pulse `en_cpu_i` for one cycle to start a program at address zero.
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- `cpu_halted_o` pulses when `ebreak` retires. A monitor must sample it every cycle rather than
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treating it as a persistent status bit.
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- `halt_cpu_i` stops execution and returns the memories to the external port. Reset before starting
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another program.
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### Running a program
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At the chip boundary, a normal test has six phases:
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1. Reset the chip and place all testbench-driven signals at idle values.
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2. Write the program into instruction SRAM through the external port.
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3. Write any initial values into data SRAM.
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4. Pulse `en_cpu_i` to start execution.
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5. Observe the halt pulse, with a bounded timeout in case the CPU is broken.
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6. Read architectural state through the external port and compare it with an independent
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prediction.
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That sequence is simple, but the timing and ownership changes create most of the verification work.
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The driver must obey the protocol, the monitor must reconstruct what actually occurred, and the
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scoreboard must not assume that driver intent became DUT behavior.
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## Testbench overview
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| File | Purpose | Member work |
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| --- | --- | --- |
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| `src/verilog/tb/cpu_if.sv` | Groups chip signals and supplies a clocking block that prevents testbench/RTL races. | Provided |
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| `src/verilog/tb/cpu_seq_item.svh` | Represents one randomized instruction and encodes it into a program word. | Complete constraints |
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| `src/verilog/tb/cpu_xbar_item.svh` | Represents external accesses and monitor observations. | Complete constraints |
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| `src/verilog/tb/cpu_sequencer.svh` | Generates programs/accesses and sends them to the driver through a mailbox. | Provided |
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| `src/verilog/tb/cpu_driver.svh` | Converts high-level requests into cycle-accurate chip pin activity. | Complete protocol tasks |
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| `src/verilog/tb/cpu_monitor.svh` | Samples the interface and turns observed behavior into transactions. | Complete delayed-read and CPU-memory reconstruction |
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| `src/verilog/tb/cpu_ref_model.svh` | Executes the supported architecture without modeling pipeline timing. | Provided; may be extended |
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| `src/verilog/tb/cpu_sb.svh` | Maintains independent state and compares DUT observations with predictions. | Complete CPU prediction and checking paths |
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| `src/verilog/tb/cpu_tb_pkg.sv` | Holds shared types, constants, helpers, and class includes. | Provided |
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| `src/verilog/tb/cpu_tb_top.sv` | Instantiates the DUT and components, runs tests, and contains assertions. | Add tests and assertions |
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| `Fall-26-Onboarding-TestPlan-Template.md` | Plan organized like the testbench: functional, chip-level, random, assertion, coverage, and bug-hunt sections. | Copy into initial and final plans |
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| `sim/behav/Include/member.include` | Lists the member CPU and testbench sources compiled by Xcelium. | Update only if filenames differ |
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| `sim/behav/Makefile` | Provides the simulation, waveform, coverage, and bug-hunt commands. | Provided |
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### How the components cooperate
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The **sequencer** decides what operation should be attempted. It sends transaction objects through
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a mailbox to the **driver**, which is the only class allowed to drive DUT inputs.
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The **monitor** independently samples signals at the chip boundary. It converts observed requests,
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responses, CPU memory operations, reset, start, and halt into transactions for the **scoreboard**.
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The monitor never asks the driver what it intended to do.
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The scoreboard keeps shadow copies of instruction and data memory. When it observes a CPU start, it
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loads those shadows into the supplied **reference model**. The model predicts architectural state
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and ordered stores without relying on DUT timing. Later monitor transactions are checked against
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those predictions.
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This separation matters. If the scoreboard used the driver's requested data as proof of what the
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DUT received, a broken driver or DUT interface could agree with the scoreboard and falsely pass.
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Good verification needs an independent observation path and an independent source of expected
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behavior.
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**Code coverage** answers “which DUT implementation structures executed?” It does not prove
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correctness by itself: tests still need expected-value checks, and uncovered RTL requires
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investigation.
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## Project stages
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### 1. Write the first test plan
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Copy [the Markdown test-plan template](Fall-26-Onboarding-TestPlan-Template.md) to
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`testplan_initial.md` and submit it before writing test cases. Keep that reviewed copy unchanged;
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make `testplan_final.md` for revisions during implementation and coverage closure. Markdown is used
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so programs, assertions, commands, and expected values remain readable and copyable. For each
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planned scenario, identify:
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- the functionality or requirement,
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- the stimulus and relevant initial state,
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- the externally observable expected result,
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- which component provides that expected result,
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- the evidence that would distinguish a DUT failure from a testbench failure.
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The first-week plan is a preliminary implementation outline, not a promise that you already
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understand the supplied coverage model. Duplicate the detailed test record and add table rows as
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needed. In the final revision, map implemented tests to the relevant functional-coverage bins and
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record what changed after simulation. Do not silently rewrite the original reasoning when results
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contradict it; the revision history is part of the DV work.
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Do not make a checklist containing only one friendly example per operation. Think about value
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classes, limits, state transitions, dependencies between adjacent operations, ownership changes,
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and interactions between otherwise-correct features. The point is to explain why the selected
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tests demonstrate the specified behavior, not to guess the golden test list.
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### 2. Set up the environment
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1. Sign the [Cadence EULA](https://eulas.ece.gatech.edu/cadence/), selecting research under advisor
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Visvesh Sathe and project SiliconJackets.
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2. Connect to `ece-rschsrv.ece.gatech.edu` using FastX, MobaXterm, or another X-capable client.
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3. Run `tcsh` to enter the C shell.
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4. Run `source /tools/software/cadence/setup.csh` to load the Cadence tools. You may add the setup
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command to `~/.my-cshrc` so it runs when you start `tcsh`.
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5. Clone this repository and enter `sim/behav`.
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Useful commands:
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```sh
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make help # list the supported targets
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make xrun # compile and run your CPU with the repeatable default seed
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make simvision # open the member-CPU waveform
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make coverage # open the member coverage database in IMC
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```
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`make xrun` reads `member.include`, creates symbolic links under `WORKSPACE`, compiles with
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Xcelium, and runs `cpu_tb_top`. The first run will stop at the earliest unfinished TODO. That is an
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onboarding checkpoint, not a syntax failure.
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### 3. Add your CPU RTL
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Copy only your SystemVerilog CPU RTL into `src/verilog/cpu/`. Do not copy the previous project's
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Makefile, memory-image flow, tests, or simulation scripts. The supplied `chip_top` expects the
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existing `cpu_top` interface. If your implementation uses additional or differently named RTL
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files, update the CPU section of `sim/behav/Include/member.include`.
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Do not modify `chip_top.sv`, `memory_controller.sv`, `sram_wrapper.sv`, or the SRAM macro as part of
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the normal onboarding solution.
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### 4. Complete protocol, monitoring, and checking
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Complete and debug one component milestone at a time:
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| Milestone | What is already supplied |
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| --- | --- |
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| Driver | Mailbox dispatch, limits, and recovery bookkeeping |
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| Monitor | Reset/start/halt recognition, protocol checks, and external writes |
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| Scoreboard | Reset, shadow writes, and a complete external-read comparison |
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| Constraints | A mix of complete examples |
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| Tests | Test lifecycle, smoke test, halt-path smoke, and helpers |
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| Assertions | One complete assertion and shared failure accounting |
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Each TODO states an observable contract without prescribing the golden implementation. Before
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writing code:
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1. Find the relevant signals in `cpu_if.sv` and the protocol requirement in this README.
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2. Decide which clocking event owns each drive or sample.
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3. Identify state that must survive between cycles and state that reset must clear.
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4. Decide how the component will fail if the DUT does not respond.
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5. Run the smallest available scenario and inspect both the log and waveform.
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Start with the driver, then the monitor, then the scoreboard. Re-run after each milestone. A
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simulation may reach several kinds of event in one scenario, so the next failure is evidence about
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the next missing runtime path—not necessarily the next numeric TODO. The supplied handlers are
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working examples of component responsibilities, not proof that the remaining behavior is correct.
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A useful mismatch reports the active test, operation, location, expected value, and actual value.
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Every wait for a DUT response must be bounded. A program timeout must record a failure, reset the
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environment, and avoid readback that would create misleading secondary errors.
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### 5. Add directed tests and assertions
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Translate the approved test plan into small, named scenarios in `cpu_tb_top.sv`. Use the supplied
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assembly and `run_directed` helpers instead of rebuilding program-loading boilerplate. Prefer a test
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whose failure points to one behavior over a long program that can fail for many unrelated reasons.
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The relevant member work is located here. The three test tasks are already called by the provided
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top-level `initial` block:
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| Work | Where to write it |
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| --- | --- |
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| Functional directed CPU programs | `run_member_directed_tests()` in `cpu_tb_top.sv` |
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| Chip-control scenarios that use a CPU program | `run_member_directed_tests()` in `cpu_tb_top.sv` |
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| Random CPU programs | `run_member_random_tests()` in `cpu_tb_top.sv` |
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| Directed and random external address-port tests | `run_member_xbar_tests()` in `cpu_tb_top.sv` |
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| Instruction constraints | Constraint blocks in `cpu_seq_item.svh` |
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| External-port constraints | Constraint blocks in `cpu_xbar_item.svh` |
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| Concurrent assertions | Bottom of `cpu_tb_top.sv`, after the supplied assertion |
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Do not add separate top-level `initial` blocks for ordinary tests. Put each scenario in the matching
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task so reset, ordering, final reporting, and the encrypted rerun remain consistent.
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Assertions check temporal protocol rules on every cycle, independent of the active program. For
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each assertion, decide:
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- the sampling clock and reset behavior,
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- whether the consequence begins immediately or on a later cycle,
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- whether a response must occur within a bounded window, and
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- how its failure contributes to the final result.
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The supplied simultaneous-read/write assertion demonstrates the reporting path. Temporarily create
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a violation for every assertion you add and retain log or waveform evidence that it fires. Revert
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the deliberate violation afterward. Add at least two assertions of your own and update
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`MEMBER_ASSERTION_COUNT`; the final summary rejects a suite that leaves this stage empty.
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### 6. Add constrained-random testing
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SystemVerilog constrained random verification generates varied inputs while excluding illegal or
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unproductive combinations. The constraint exercises intentionally use three levels:
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- **Provided examples:** `c_opcode`, `c_reg_bias`, `c_imm_unused`, `c_no_branch_at_end`, `c_align`,
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and `c_reg_read_only` demonstrate membership, weighted distribution, implication, and bit
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constraints. Read them and explain what each one accomplishes.
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- **Partial constraints:** `c_imm_range`, `c_branch_target`, and `c_valid_window` contain a legal
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starting condition. Complete the missing part using the nearby contract.
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- **Open constraints:** design `c_mem_align`, `c_branch_taken_bias`, and `c_data_corners` from the
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required behavior and supplied coverage model.
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For each constraint you complete, document the invalid state it removes, the useful distribution
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or dependency it encourages, and any legal behavior it makes unreachable.
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Random stimulus is valuable only when it is reproducible and checked. Generated instructions are
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printed by default. The Makefile also controls Xcelium's seed:
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```sh
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make xrun SEED=1 # repeat a known run
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make xrun SEED=random # ask Xcelium to choose a new seed
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```
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For a random run, record the numeric `SVSEED` printed by Xcelium and rerun with that number. Reset
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between random programs, label each iteration, and ensure the monitor/scoreboard path checks every
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relevant result. A seed without the generated program and failing iteration is weak evidence.
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### 7. Report DUT code coverage and revise the plan
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Run the complete member suite, then inspect coverage:
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```sh
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make xrun
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make coverage
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```
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Completion requires:
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- at least 98% code coverage under `cpu_tb_top.dut`,
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- a revised test plan containing tests added during coverage closure.
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Coverage is a question generator. An uncovered item may reveal missing stimulus, an impossible
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scenario, a monitor sampling error, or a mistaken plan. Investigate which one applies before adding
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another test or excluding the item.
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### 8. Characterize the encrypted CPU
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After your own CPU passes, run the same completed testbench against the provided encrypted CPU:
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```sh
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make bug_hunt # compile the encrypted CPU and run the complete suite
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make bug_hunt_simvision # open the encrypted-CPU waveform
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```
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The encrypted CPU contains **three** injected bugs, and you are required to find and characterize
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**all three**. This stage demonstrates why constrained-random testing is useful: a varied but legal
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stream can expose an interaction that a short directed checklist missed. Your bugs must
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first be observed in your constrained-random phase, not chosen from a disclosed trigger or written
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as a directed test in advance.
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```sh
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make bug_hunt SEED=random # explore; record Xcelium's numeric SVSEED
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make bug_hunt SEED=12345 # reproduce an interesting run
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```
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`make bug_hunt` deterministically assigns one of three encrypted CPUs from the local Unix
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username and prints the selected variant before compiling. The same username receives the same
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variant on every run, while the three variants distribute different additional corner cases
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across the cohort.
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Run multiple seeds, retain the first reproducible failure, and then reduce it into a focused
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reproducer. `make bug_hunt` disables stop-on-first-scoreboard-error so the run can collect useful
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evidence. It writes `bug_hunt.log` and `bug_hunt_waves.shm`, leaving the member run's
|
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`simulation.log` and `waves.shm` intact. Do not modify, replace, decrypt, or attempt to recover the
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protected RTL.
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For each selected bug, record the minimum failing program that would reproduce the error. For each bug, submit:
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1. A description of the bug, with the expected and actual behavior of the CPU.
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2. Waveform evidence at readable chip-level signals.
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3. The minimum failing program that triggers the bug and experiments used to separate the trigger from nearby possibilities.
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## Deliverables
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You may submit online as one archive or complete an in-person checkoff at a work session. Include:
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1. `testplan_initial.md` and `testplan_final.md`; a rendered PDF of each is optional.
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- `testplan_initial.md` **is due Sunday, September 27 at 11:59pm, no exceptions.**
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- You will submit `testplan_final.md`, with any revisions, **on Sunday, October 4 at 11:59pm, no exceptions.**
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2. The completed driver, monitor, scoreboard, sequence items, and top-level testbench (tb folder).
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3. `simulation.log` showing the member CPU suite passing.
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4. An IMC screenshot showing at least 98% DUT code coverage.
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5. Evidence that each added assertion detects its intended violation.
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6. Encrypted-CPU bug report first found through constrained random, with its numeric seed,
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failing iteration, minimized program, and waveform evidence for all three bugs.
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**Deliverables #2-8 are due Sunday, October 4 at 11:59pm, no exceptions.**
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For online submissions, send the archive to the Discord account **sjcheckoffs** (SiliconJackets
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Checkoffs). In-person checkoffs at work sessions are preferred.
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### Build the submission archive
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Run the complete member suite, your automatically assigned encrypted-CPU suite, and coverage export
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before packaging (make sure you have everything):
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```sh
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make submission
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```
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(need to `cd` back into the root directory).
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## Submission disclaimer
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- Submissions after 11:59 p.m. on the announced deadline will not be accepted.
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- Verify the archive before the deadline; corrected late submissions are not accepted.
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- You may collaborate on concepts and debugging methods, but you may not share code or bug triggers.
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- Using AI to understand language or verification concepts is acceptable. Submitting generated code
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or a generated bug report that you cannot justify from your own plan, logs, and waveforms is not.
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||||
- Do not share ECE server access. Request and test access early.
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## Resources
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||||
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||||
### SystemVerilog classes
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||||
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||||
- [ChipVerify: SystemVerilog Classes](https://www.chipverify.com/systemverilog/systemverilog-class)
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||||
- [Doulos: SystemVerilog Classes Tutorial](https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-classes-tutorial/)
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||||
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||||
### Constrained random verification
|
||||
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||||
- [SystemVerilog Randomization](https://www.chipverify.com/systemverilog/systemverilog-randomization)
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||||
- [SystemVerilog Constraints](https://www.chipverify.com/systemverilog/systemverilog-constraints)
|
||||
- [Constraint Random Verification](https://www.chipverify.com/verification/constraint-random-verification)
|
||||
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||||
### RTL code coverage
|
||||
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||||
- [Code Coverage](https://www.chipverify.com/verification/code-coverage)
|
||||
|
||||
### SystemVerilog assertions
|
||||
|
||||
- [Doulos: Assertions Tutorial](https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-assertions-tutorial/)
|
||||
- [systemverilog.io: SVA Basics](https://www.systemverilog.io/verification/sva-basics/)
|
||||
|
||||
### Clocking blocks
|
||||
|
||||
- [Doulos: Clocking Tutorial](https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-clocking-tutorial/)
|
||||
- [ChipVerify: Clocking Blocks, Part 1](https://www.chipverify.com/systemverilog/systemverilog-clocking-blocks)
|
||||
- [ChipVerify: Clocking Blocks, Part 2](https://www.chipverify.com/systemverilog/systemverilog-clocking-blocks-part2)
|
||||
|
||||
### Mailboxes and processes
|
||||
|
||||
- [SystemVerilog Mailboxes](https://www.chipverify.com/systemverilog/systemverilog-mailbox)
|
||||
- [SystemVerilog fork/join](https://www.chipverify.com/systemverilog/systemverilog-fork-join-any)
|
||||
|
||||
### RISC-V
|
||||
|
||||
- [The RISC-V Instruction Set Manual, Volume I](https://riscv.org/technical/specifications/)
|
||||
|
||||
## Questions and contacts
|
||||
|
||||
Ask questions in the `onboarding-help` discussion channel on the
|
||||
[Discord server](https://discord.com/invite/swK5QnTt4j), or contact a DV lead:
|
||||
|
||||
| Name | Discord | Email |
|
||||
| --- | --- | --- |
|
||||
| Kevin Luo | elmothefrog | kluo78@gatech.edu |
|
||||
| Khai Tran | khxit | ktran333@gatech.edu |
|
||||
| Mai Bharathi | moose8511 | mbharathi7@gatech.edu |
|
||||
| Matthew Nichols | fastbreakd | mi72@gatech.edu |
|
||||
| Ethan Huang | nathanhueg | ethanhuang@gatech.edu |
|
||||
Reference in New Issue
Block a user