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Ethan Huang
2026-09-20 21:43:19 -04:00
commit 5ab1714b67
39 changed files with 5456 additions and 0 deletions
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sim/behav/Include/bug_hunt.include
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// Provided chip RTL
../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
../../src/verilog/sram_wrapper.sv
../../src/verilog/memory_controller.sv
../../src/verilog/chip_top.sv
// Encrypted bug-hunt CPU
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/cpu_pkg.svp
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/reg_file.svp
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/fetch.svp
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/cpu_top.svp
// The same member testbench used against the member CPU
../../src/verilog/tb/cpu_if.sv
../../src/verilog/tb/cpu_seq_item.svh
../../src/verilog/tb/cpu_xbar_item.svh
../../src/verilog/tb/cpu_ref_model.svh
../../src/verilog/tb/cpu_sequencer.svh
../../src/verilog/tb/cpu_driver.svh
../../src/verilog/tb/cpu_monitor.svh
../../src/verilog/tb/cpu_sb.svh
../../src/verilog/tb/cpu_tb_pkg.sv
../../src/verilog/tb/cpu_tb_top.sv
sim/behav/Include/member.include
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// Provided chip RTL
../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
../../src/verilog/sram_wrapper.sv
../../src/verilog/memory_controller.sv
../../src/verilog/chip_top.sv
// TODO: Your CPU RTL. Update this section with your added files.
../../src/verilog/cpu/cpu_pkg.sv
../../src/verilog/cpu/reg_file.sv
../../src/verilog/cpu/fetch.sv
../../src/verilog/cpu/cpu_top.sv
// Member testbench
../../src/verilog/tb/cpu_if.sv
../../src/verilog/tb/cpu_seq_item.svh
../../src/verilog/tb/cpu_xbar_item.svh
../../src/verilog/tb/cpu_ref_model.svh
../../src/verilog/tb/cpu_sequencer.svh
../../src/verilog/tb/cpu_driver.svh
../../src/verilog/tb/cpu_monitor.svh
../../src/verilog/tb/cpu_sb.svh
../../src/verilog/tb/cpu_tb_pkg.sv
../../src/verilog/tb/cpu_tb_top.sv
sim/behav/Makefile
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# Cadence Xcelium / SimVision / IMC flow
INCLUDE_FILE_NAME ?= member.include
TOP ?= cpu_tb_top
PYTHON ?= python3
IMC ?= /tools/software/cadence/vmanageragl/25.09.020/tools.lnx86/vmgr/bin/imc
CURRENT_DIR := $(shell pwd)
WORKSPACE := $(CURRENT_DIR)/WORKSPACE
# The encrypted RTL requires SIM to select its simulation-safe declarations.
XRUN_FLAGS = -64bit -sv -linedebug -access +rwc \
-timescale 1ns/10ps +define+SIM=1 +incdir+sym_links \
-coverage all -licqueue -covoverwrite
SIM_PLUSARGS ?=
SEED ?= 1
LOGFILE ?= simulation.log
WAVE_PLUSARGS ?=
COV_TEST ?= member
# Assign each Unix username to one of the three encrypted bug-hunt CPUs.
# Summing the username bytes keeps the mapping deterministic and portable;
# BUG_HUNT_VARIANT remains overridable for staff validation.
BUG_HUNT_USER ?= $(shell id -un)
BUG_HUNT_VARIANT ?= $(shell printf '%s' '$(BUG_HUNT_USER)' | od -An -tu1 | \
awk '{ for (i = 1; i <= NF; i++) sum += $$i } END { print sum % 3 }')
.PHONY: help clean link xrun bug_hunt simvision bug_hunt_simvision coverage run_and_view
help:
@echo " make xrun [SEED=n] run your CPU"
@echo " make bug_hunt [SEED=n|random] run the encrypted CPU and collect failures"
@echo " make simvision open the member-CPU waveform"
@echo " make bug_hunt_simvision open the encrypted-CPU waveform"
@echo " make coverage open the member coverage database"
@echo " make clean remove generated simulation files"
@echo " selected bug-hunt variant: $(BUG_HUNT_VARIANT) (user $(BUG_HUNT_USER))"
clean:
@rm -rf $(WORKSPACE)
link:
@mkdir -p $(WORKSPACE)/sym_links
@rm -rf $(WORKSPACE)/sym_links/*
@BUG_HUNT_VARIANT=$(BUG_HUNT_VARIANT) $(PYTHON) link_files.py $(INCLUDE_FILE_NAME)
xrun: link
cd $(WORKSPACE) && \
xrun $(XRUN_FLAGS) -svseed $(SEED) -f sym_links/sim_no_path.include \
-top $(TOP) -covtest $(COV_TEST) -logfile $(LOGFILE) \
+SEED_LABEL=$(SEED) $(WAVE_PLUSARGS) $(SIM_PLUSARGS)
bug_hunt:
@echo "Bug-hunt variant $(BUG_HUNT_VARIANT) selected for $(BUG_HUNT_USER)"
@rm -rf $(WORKSPACE)/xcelium.d
$(MAKE) xrun INCLUDE_FILE_NAME=bug_hunt.include \
LOGFILE=bug_hunt.log WAVE_PLUSARGS=+BUG_HUNT_WAVES COV_TEST=bug_hunt \
BUG_HUNT_VARIANT=$(BUG_HUNT_VARIANT) \
SIM_PLUSARGS="$(SIM_PLUSARGS) +NO_STOP_ON_ERROR"
simvision:
cd $(WORKSPACE) && simvision waves.shm &
bug_hunt_simvision:
cd $(WORKSPACE) && simvision bug_hunt_waves.shm &
coverage:
cd $(WORKSPACE) && $(IMC) -load cov_work/scope/$(COV_TEST) -load_refinement $(CURRENT_DIR)/exclusions.vRefine &
run_and_view: xrun simvision
.DEFAULT_GOAL := run_and_view
sim/behav/exclusions.vRefine
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<refinement-file-root>
<information comment-version="2" creation-time="Sat 19 Sep 2026 21:58:30 EDT" creator="kluo78" csCheck="false" save-ref-method="seq" tool-version="Cadence Verisium Manager25.09" rules-signature-c="5afb555bef40c3c4e3e350ecedd8410">
<ucm-files>
<ucm-file domain="icc" modelCheckSum="1706311643" path="cov_work/scope/icc_65b43fdb_648f2f2c.ucm"></ucm-file>
</ucm-files>
<ccf-files></ccf-files>
</information>
<rules>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/addr_i/1" entityType="toggle-bit" excTime="1789867536" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/addr_i/0" entityType="toggle-bit" excTime="1789867539" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/core_isram_rdata/3" entityType="toggle-bit" excTime="1789867626" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/core_isram_rdata/2" entityType="toggle-bit" excTime="1789867629" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/mem_ctrl/core_isram_rdata_o/3" entityType="toggle-bit" excTime="1789867720" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/mem_ctrl/core_isram_rdata_o/2" entityType="toggle-bit" excTime="1789867724" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/mem_ctrl/addr_i/0" entityType="toggle-bit" excTime="1789867729" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/mem_ctrl/addr_i/1" entityType="toggle-bit" excTime="1789867732" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/isram_rdata_i/2" entityType="toggle-bit" excTime="1789869318" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/isram_rdata_i/3" entityType="toggle-bit" excTime="1789869321" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/instr_o/2" entityType="toggle-bit" excTime="1789869334" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/instr_o/3" entityType="toggle-bit" excTime="1789869337" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/0" entityType="toggle-bit" excTime="1789869393" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/1" entityType="toggle-bit" excTime="1789869396" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/31" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/30" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/29" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/28" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
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<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/26" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/25" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/24" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/23" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/22" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/21" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/20" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/19" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/18" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/17" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
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<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/pc_o/12" entityType="toggle-bit" excTime="1789869414" name="exclude" reviewer="1" user="0" vscope="default"></rule>
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<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/next_pc/1" entityType="toggle-bit" excTime="1789869442" name="exclude" reviewer="1" user="0" vscope="default"></rule>
<rule ccType="inst" domain="icc" entityName="cpu_tb_top/dut/cpu/u_fetch/next_pc/0" entityType="toggle-bit" excTime="1789869442" name="exclude" reviewer="1" user="0" vscope="default"></rule>
</rules>
<cache-map>
<cache-entry key="0" value="kluo78"></cache-entry>
<cache-entry key="1" value="unknown"></cache-entry>
</cache-map>
</refinement-file-root>
sim/behav/link_files.py
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import os
import re
import sys
if len(sys.argv) != 2:
print("Usage: python3 link_files.py <include_file_name>")
sys.exit(1)
input_file = os.path.join("Include", sys.argv[1])
workspace_dir = "WORKSPACE"
sym_links_dir = os.path.join(workspace_dir, "sym_links")
output_file = os.path.join(sym_links_dir, "sim_no_path.include")
print(f"looking in file {input_file}")
if not os.path.isfile(input_file):
print(f"Error: include list does not exist: {input_file}")
sys.exit(1)
os.makedirs(sym_links_dir, exist_ok=True)
had_error = False
seen_links = {}
with open(input_file, "r", encoding="utf-8") as input_fp:
with open(output_file, "w", encoding="utf-8") as output_fp:
for raw_line in input_fp:
line = raw_line.strip()
if not line or line.startswith("//"):
output_fp.write(line + "\n")
continue
match = re.match(r"^\s*(\S+)\s*$", line)
if not match:
print(f"Error: invalid file path in line: {line}")
had_error = True
continue
file_path = os.path.expandvars(match.group(1))
if not os.path.exists(file_path):
print(f"Error: file does not exist: {file_path}")
had_error = True
continue
basename = os.path.basename(file_path)
absolute_path = os.path.abspath(file_path)
if basename in seen_links and seen_links[basename] != absolute_path:
print(
f"Error: duplicate filename {basename} refers to both "
f"{seen_links[basename]} and {absolute_path}"
)
had_error = True
continue
seen_links[basename] = absolute_path
link_path = os.path.join(sym_links_dir, basename)
if os.path.lexists(link_path):
os.unlink(link_path)
os.symlink(absolute_path, link_path)
# Header files are included by cpu_tb_pkg rather than compiled alone.
if not file_path.endswith(".svh"):
output_fp.write(f"sym_links/{basename}\n")
if had_error:
sys.exit(1)