From 5b15f9a0191dacc71c8fa642bad94609a9acd9c5 Mon Sep 17 00:00:00 2001
From: dylanbenzi <dylanbenzi@gmail.com>
Date: Sat, 26 Sep 2026 15:30:20 -0400
Subject: [PATCH] add rtl files to sim include

---
 sim/behav/Include/member.include | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sim/behav/Include/member.include b/sim/behav/Include/member.include
index 94cae7f..68f6168 100644
--- a/sim/behav/Include/member.include
+++ b/sim/behav/Include/member.include
@@ -9,6 +9,10 @@
 ../../src/verilog/cpu/reg_file.sv
 ../../src/verilog/cpu/fetch.sv
 ../../src/verilog/cpu/cpu_top.sv
+../../src/verilog/cpu/control_unit.sv
+../../src/verilog/cpu/decode.sv
+../../src/verilog/cpu/execute.sv
+../../src/verilog/cpu/sign_extend.sv
 
 // Member testbench
 ../../src/verilog/tb/cpu_if.sv