From ec969afb4710e2d19dc8a1db7d10467f46de61de Mon Sep 17 00:00:00 2001 From: "Luo, Kevin" Date: Wed, 23 Sep 2026 11:15:40 -0400 Subject: [PATCH] cpu_sb.svh todo comment fix --- src/verilog/tb/cpu_sb.svh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/verilog/tb/cpu_sb.svh b/src/verilog/tb/cpu_sb.svh index 167b440..9a58a90 100644 --- a/src/verilog/tb/cpu_sb.svh +++ b/src/verilog/tb/cpu_sb.svh @@ -148,7 +148,7 @@ class cpu_sb #(int DataSize=32, int AddrSize=14); // TODO: Load both expected memories through the reference-model // API and run it with MAX_REF_INSTR as its bound. Save predicted // registers and the ordered store queue, reset per-program counters, - // mark the program active, and sample the executed instruction trace. + // and mark the program active. fail("CPU_START prediction is not implemented"); end @@ -180,8 +180,8 @@ class cpu_sb #(int DataSize=32, int AddrSize=14); // A normal halt must finish all expected CPU activity CPU_HALT: begin // TODO: Check that every expected store was observed, compare - // final data memory with the reference model, sample program - // coverage, and mark the program inactive. + // final data memory with the reference model, and mark the + // program inactive. fail("CPU_HALT checking is not implemented"); end