Update README.md

add tb arch resources
This commit is contained in:
Luo, Kevin
2026-09-21 14:41:25 -04:00
committed by GitHub Enterprise
parent a89d72e1ae
commit f1ffe1e781
+6
View File
@@ -385,6 +385,12 @@ make submission
## Resources ## Resources
### Testbench architecture
- [VerificationGuide: SystemVerilog](https://verificationguide.com/systemverilog/)
- [VerificationGuide: SystemVerilog Testbench](https://verificationguide.com/systemverilog/systemverilog-testbench/)
- [VerificationGuide: SystemVerilog Adder Testbench Example](https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-adder/)
- [ChipVerify: SystemVerilog Simple Testbench](https://chipverify.com/systemverilog/systemverilog-simple-testbench)
### SystemVerilog classes ### SystemVerilog classes
- [ChipVerify: SystemVerilog Classes](https://www.chipverify.com/systemverilog/systemverilog-class) - [ChipVerify: SystemVerilog Classes](https://www.chipverify.com/systemverilog/systemverilog-class)