// Provided chip RTL
../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
../../src/verilog/sram_wrapper.sv
../../src/verilog/memory_controller.sv
../../src/verilog/chip_top.sv

// Encrypted bug-hunt CPU
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/cpu_pkg.svp
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/reg_file.svp
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/fetch.svp
../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/cpu_top.svp

// The same member testbench used against the member CPU
../../src/verilog/tb/cpu_if.sv
../../src/verilog/tb/cpu_seq_item.svh
../../src/verilog/tb/cpu_xbar_item.svh
../../src/verilog/tb/cpu_ref_model.svh
../../src/verilog/tb/cpu_sequencer.svh
../../src/verilog/tb/cpu_driver.svh
../../src/verilog/tb/cpu_monitor.svh
../../src/verilog/tb/cpu_sb.svh
../../src/verilog/tb/cpu_tb_pkg.sv
../../src/verilog/tb/cpu_tb_top.sv