module sign_extend (
    input logic [31:0] instr_i,
    input logic [ 1:0] imm_src_i,

    output logic [31:0] imm_ext_o,
    output logic instr_invld_o
);

  always_comb begin
    imm_ext_o = '0;
    instr_invld_o = 1'b0;
    case (imm_src_i)
      2'b00:   imm_ext_o = {{20{instr_i[31]}}, instr_i[31:20]};
      2'b01:   imm_ext_o = {{20{instr_i[31]}}, instr_i[31:25], instr_i[11:7]};
      2'b10:   imm_ext_o = {{20{instr_i[31]}}, instr_i[7], instr_i[30:25], instr_i[11:8], 1'b0};
      default: instr_invld_o = 1'b1;
    endcase
  end

endmodule