design-verification-onboarding-F26/testplan_final.md

Fall 2026 DV Onboarding Test Plan

NOTE: THIS IS A TEMPLATE FOR YOU TO FOLLOW. THIS IS NOT A COMPREHENSIVE TESTPLAN. YOU NEED TO EXTEND IT.

Document information

Field	Value
Verification engineer	Name, Discord username, GT username
Plan revision	Initial / Final
Date	YYYY-MM-DD

Revision history

Revision	Date	Changes
Initial	YYYY-MM-DD	Initial planned tests
Final	YYYY-MM-DD

1. Functional tests

Functional-test summary

Test ID	Test name	Functionality being tested	Expected result	Status
1.1	test_name			Planned
1.2				Planned
1.3				Planned

Functional-test details

1.1 — test_name

Functionality:

Initial state:

• Registers:
• Data memory:
• Other setup:

Program:

prog = '{
  // asm_instr(.op(...), .rd(...), .rs1(...), .rs2(...), .imm(...)),
  EBREAK_WORD
};

Expected result:

Register or memory word	Expected value	Calculation or explanation
x__	32'h________
dmem[__]	32'h________

Pass criteria:

Final result:

2. Constrained-random tests

Instruction constraints

Constraint	Provided, partial, or open	Behavior and purpose	Final implementation summary
c_opcode	Provided		No member change
c_reg_bias	Provided		No member change
c_imm_range	Partial
c_mem_align	Open
c_imm_unused	Provided		No member change
c_branch_target	Partial
c_no_branch_at_end	Provided		No member change
c_branch_taken_bias	Open

External-port constraints

Constraint	Provided, partial, or open	Behavior and purpose	Final implementation summary
c_align	Provided		No member change
c_valid_window	Partial
c_reg_read_only	Provided		No member change
c_data_corners	Open

Random-program test

Item	Plan
Number of programs per seed
Program-length range
Information logged for reproduction	Numeric SVSEED, iteration, and complete generated program

Implementation outline:

// Write the intended loop and lifecycle using seqr.gen_program(...).

3. Assertions

Assertion summary

Assertion ID/name	Behavior checked	When it is sampled/disabled	Activating test
4.1 / PROPERTY_NAME
4.2 / PROPERTY_NAME

4.1 — PROPERTY_NAME

Timing requirement in words:

PROPERTY_NAME:
  assert property (@(posedge clk) disable iff (rst)
    /* property expression */)
  else assertion_fail("descriptive failure message");

Evidence that it detects a violation:

4.2 — PROPERTY_NAME

Timing requirement in words:

PROPERTY_NAME:
  assert property (@(posedge clk) disable iff (rst)
    /* property expression */)
  else assertion_fail("descriptive failure message");

Evidence that it detects a violation:

4. Encrypted CPU Bug Hunt

Random discovery

Field	Evidence
Discovery command	make bug_hunt SEED=random
Numeric SVSEED
Failing iteration
First failure message
Reproduction command	make bug_hunt SEED=________
Reproduces consistently?	Yes / No

Original failing program:

prog = '{
  // Paste original generated sequence
  EBREAK_WORD
};

Expected vs. actual

Instruction / event	Expected	Actual	Cycle/time

First architectural divergence:

Minimization

Minimized reproducer:

prog = '{
  // Smallest sequence that still fails
  EBREAK_WORD
};

Waveform evidence

Include a screenshot showing the offending instruction and the first incorrect architectural result.

Conclusion

Trigger:

Expected behavior:

Observed behavior:

Behavioral characterization: