24 lines
869 B
Plaintext
24 lines
869 B
Plaintext
// Provided chip RTL
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../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
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../../src/verilog/sram_wrapper.sv
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../../src/verilog/memory_controller.sv
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../../src/verilog/chip_top.sv
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// Encrypted bug-hunt CPU
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../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/cpu_pkg.svp
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../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/reg_file.svp
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../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/fetch.svp
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../../src/verilog/bug_hunt_cpu_${BUG_HUNT_VARIANT}/cpu_top.svp
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// The same member testbench used against the member CPU
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../../src/verilog/tb/cpu_if.sv
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../../src/verilog/tb/cpu_seq_item.svh
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../../src/verilog/tb/cpu_xbar_item.svh
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../../src/verilog/tb/cpu_ref_model.svh
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../../src/verilog/tb/cpu_sequencer.svh
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../../src/verilog/tb/cpu_driver.svh
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../../src/verilog/tb/cpu_monitor.svh
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../../src/verilog/tb/cpu_sb.svh
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../../src/verilog/tb/cpu_tb_pkg.sv
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../../src/verilog/tb/cpu_tb_top.sv
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