28 lines
892 B
Plaintext
28 lines
892 B
Plaintext
// Provided chip RTL
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../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
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../../src/verilog/sram_wrapper.sv
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../../src/verilog/memory_controller.sv
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../../src/verilog/chip_top.sv
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// TODO: Your CPU RTL. Update this section with your added files.
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../../src/verilog/cpu/cpu_pkg.sv
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../../src/verilog/cpu/reg_file.sv
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../../src/verilog/cpu/fetch.sv
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../../src/verilog/cpu/cpu_top.sv
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../../src/verilog/cpu/control_unit.sv
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../../src/verilog/cpu/decode.sv
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../../src/verilog/cpu/execute.sv
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../../src/verilog/cpu/sign_extend.sv
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// Member testbench
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../../src/verilog/tb/cpu_if.sv
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../../src/verilog/tb/cpu_seq_item.svh
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../../src/verilog/tb/cpu_xbar_item.svh
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../../src/verilog/tb/cpu_ref_model.svh
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../../src/verilog/tb/cpu_sequencer.svh
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../../src/verilog/tb/cpu_driver.svh
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../../src/verilog/tb/cpu_monitor.svh
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../../src/verilog/tb/cpu_sb.svh
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../../src/verilog/tb/cpu_tb_pkg.sv
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../../src/verilog/tb/cpu_tb_top.sv
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