diff --git a/src/verilog/cpu/cpu_top.sv b/src/verilog/cpu/cpu_top.sv
index eef71b7..638b42a 100644
--- a/src/verilog/cpu/cpu_top.sv
+++ b/src/verilog/cpu/cpu_top.sv
@@ -37,6 +37,25 @@ module cpu_top (
   logic [31:0] current_pc;
   logic instr_vld;
 
+  logic alu_zero;
+  logic result_src;
+  logic mem_write;
+  logic alu_src;
+  logic [1:0] alu_control;
+  logic [31:0] imm_ext;
+  logic [31:0] rs1_data;
+  logic [31:0] rs2_data;
+  logic instr_invld_decode;
+  logic [31:0] alu_result;
+
+  logic [31:0] pc_target;
+
+  logic branch_vld;
+  logic [9:0] branch_trgt;
+  logic branch_taken;
+
+  logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
+
   assign stall_core = halted_o | ~en_i;  //when else would you stall?
 
   // === Instruction Fetch === //
@@ -58,17 +77,6 @@ module cpu_top (
       .branch_taken_i(branch_taken)
   );
 
-  logic alu_zero;
-  logic result_src;
-  logic mem_write;
-  logic alu_src;
-  logic [1:0] alu_control;
-  logic [31:0] imm_ext;
-  logic [31:0] rs1_data;
-  logic [31:0] rs2_data;
-  logic instr_invld_decode;
-  logic [31:0] alu_result;
-
 
   assign dsram_en_o = 1'b1;
   assign dsram_wdata_o = rs2_data;
@@ -93,11 +101,6 @@ module cpu_top (
       .ebreak_o(halted_o)
   );
 
-  logic [31:0] pc_target;
-
-  logic branch_vld;
-  logic [9:0] branch_trgt;
-  logic branch_taken;
 
   always_comb begin
     if (pc_target[31:12] == '0) begin
@@ -123,6 +126,5 @@ module cpu_top (
   );
 
   assign dsram_addr_o = alu_result[11:2];
-  logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
 
 endmodule