From 4723f7ffaab97274e9db6aa6073f59c9aa41b6a3 Mon Sep 17 00:00:00 2001 From: dylanbenzi Date: Sun, 20 Sep 2026 18:45:42 -0400 Subject: [PATCH] update load stall condition --- src/verilog/cpu/cpu_top.sv | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/verilog/cpu/cpu_top.sv b/src/verilog/cpu/cpu_top.sv index 2003964..bae7e14 100644 --- a/src/verilog/cpu/cpu_top.sv +++ b/src/verilog/cpu/cpu_top.sv @@ -59,8 +59,16 @@ module cpu_top ( logic ebreak_latch; logic load_stall; + logic load_stall_cycle; - assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall; //when else would you stall? + assign stall_core = ebreak_latch | halted_o | ~en_i; + + always_ff @(posedge clk_i) begin + if (load_stall & ~load_stall_cycle) begin + stall_core <= 1'b1; + load_stall_cycle <= 1'b0; + end else if (load_stall & load_stall_cycle) stall_core <= 1'b0; + end // === Instruction Fetch === // // certain ports are tied off bc they depend on modulees you need to implement.