dylan/digital-design-onboarding-F26-main
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial Commit

Browse Source
This commit is contained in:
Konstantin Gaydev
2026-09-04 11:40:42 -04:00
committed by Cooper Shaw
commit 49a639f69a
76 changed files with 3766 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tests/add/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/add/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/add/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000014
00000006
0000001a
00000014
ffffffff
fffffffe
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/add/program.asm
+8
View File
@@ -0,0 +1,8 @@
_start:
addi x1, x0, 20
addi x2, x0, 6
add x3, x1, x2
add x4, x1, x0
addi x5, x0, -1
add x6, x5, x5
ebreak
tests/addi/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/addi/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/addi/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000007
00000004
000007ff
fffff800
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/addi/program.asm
+6
View File
@@ -0,0 +1,6 @@
_start:
addi x1, x0, 7
addi x2, x1, -3
addi x3, x0, 2047
addi x4, x0, -2048
ebreak
tests/branch_not_taken/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/branch_not_taken/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/branch_not_taken/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000001
00000001
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/branch_not_taken/program.asm
+7
View File
@@ -0,0 +1,7 @@
_start:
addi x1, x0, 1
beq x1, x0, target
addi x2, x0, 1
target:
addi x3, x0, 2
ebreak
tests/branch_taken/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/branch_taken/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/branch_taken/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000000
00000000
00000002
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/branch_taken/program.asm
+7
View File
@@ -0,0 +1,7 @@
_start:
addi x1, x0, 0
beq x1, x0, taken
addi x2, x0, 1
taken:
addi x3, x0, 2
ebreak
tests/complex1/data.hex
+6
View File
@@ -0,0 +1,6 @@
00000000
00000003
0000002a
00000011
00000008
00000063
tests/complex1/expected_data.hex
+8
View File
@@ -0,0 +1,8 @@
00000000
00000003
0000002a
00000011
00000008
00000063
xxxxxxxx
00000063
tests/complex1/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000018
00000000
00000063
00000063
ffffffc7
00000001
00000001
00000004
0000001f
00000000
00000063
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
tests/complex1/program.asm
+31
View File
@@ -0,0 +1,31 @@
_start:
addi x1, x0, 4
addi x2, x0, 5
addi x7, x0, 1
addi x8, x0, 4
addi x9, x0, 31
lw x3, 0(x1)
add x1, x1, x8
addi x2, x2, -1
maxloop:
lw x4, 0(x1)
sub x5, x3, x4
srl x6, x5, x9
beq x6, x0, keep
add x3, x0, x4
keep:
add x1, x1, x8
sub x2, x2, x7
beq x2, x0, done
beq x0, x0, maxloop
done:
sw x3, 28(x0)
lw x11, 28(x0)
beq x11, x3, pass
addi x31, x0, 0
ebreak
pass:
addi x31, x0, 1
ebreak
tests/complex2/data.hex
+6
View File
@@ -0,0 +1,6 @@
00000000
0000000b
00000016
00000021
0000002c
00000037
tests/complex2/expected_data.hex
+13
View File
@@ -0,0 +1,13 @@
00000000
0000000b
00000016
00000021
0000002c
00000037
xxxxxxxx
xxxxxxxx
00000037
0000002c
00000021
00000016
0000000b
tests/complex2/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000004
00000020
ffffffff
00000005
00000000
00000004
00000002
0000000b
00000001
00000010
00000030
00000000
00000037
0000000b
00000037
0000000b
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
tests/complex2/program.asm
+36
View File
@@ -0,0 +1,36 @@
_start:
addi x1, x0, 4
addi x2, x0, 32
addi x3, x0, 4
addi x4, x0, 0
addi x7, x0, 2
addi x9, x0, 1
revloop:
sll x5, x3, x7
add x6, x1, x5
lw x8, 0(x6)
sll x10, x4, x7
add x11, x2, x10
sw x8, 0(x11)
addi x4, x4, 1
addi x3, x3, -1
addi x12, x3, 1
beq x12, x0, done
beq x0, x0, revloop
done:
lw x13, 32(x0)
lw x14, 48(x0)
addi x15, x0, 55
beq x13, x15, chk2
addi x31, x0, 0
ebreak
chk2:
addi x16, x0, 11
beq x14, x16, pass
addi x31, x0, 0
ebreak
pass:
addi x31, x0, 1
ebreak
tests/ebreak/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/ebreak/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/ebreak/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/ebreak/program.asm
+2
View File
@@ -0,0 +1,2 @@
_start:
ebreak
tests/lw/data.hex
+3
View File
@@ -0,0 +1,3 @@
00000000
000000aa
cafef00d
tests/lw/expected_data.hex
+3
View File
@@ -0,0 +1,3 @@
00000000
000000aa
cafef00d
tests/lw/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000000
000000aa
cafef00d
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/lw/program.asm
+5
View File
@@ -0,0 +1,5 @@
_start:
lw x1, 0(x0)
lw x2, 4(x0)
lw x3, 8(x0)
ebreak
tests/mock/chip_top_mock.sv
+55
View File
@@ -0,0 +1,55 @@
// Verification-infrastructure mock. This is not a processor model.
// It implements the debug memory map and halts one cycle after CPU enable so
// the ebreak test can exercise the complete Makefile/testbench path.
module chip_top (
input logic clk_i,
input logic rst_i,
input logic en_cpu_i,
input logic halt_cpu_i,
output logic cpu_halted_o,
// Crossbar Interface to memory + regfile
input logic [13:0] addr_i,
input logic [31:0] wdata_i,
input logic w_en_i,
input logic r_en_i,
output logic [31:0] rdata_o,
output logic rready_o
);
logic [31:0] isram [0:1023];
logic [31:0] dsram [0:1023];
logic [31:0] regs [0:31];
integer i;
always_ff @(posedge clk_i) begin
if (rst_i) begin
cpu_halted_o <= 1'b0;
for (i = 0; i < 32; i++)
regs[i] <= 32'd0;
end else begin
if (en_cpu_i || halt_cpu_i)
cpu_halted_o <= 1'b1;
if (!en_cpu_i && w_en_i) begin
case (addr_i[13:12])
2'b00: isram[addr_i[11:2]] <= wdata_i;
2'b01: dsram[addr_i[11:2]] <= wdata_i;
default: ;
endcase
end
end
end
always_comb begin
rready_o = !en_cpu_i && (w_en_i || r_en_i);
rdata_o = 32'd0;
if (!en_cpu_i && r_en_i) begin
case (addr_i[13:12])
2'b00: rdata_o = isram[addr_i[11:2]];
2'b01: rdata_o = dsram[addr_i[11:2]];
2'b10: rdata_o = regs[addr_i[6:2]];
default: rdata_o = 32'd0;
endcase
end
end
endmodule
tests/sll/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/sll/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/sll/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000001
00000004
00000010
0000001f
80000000
00000000
00000001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/sll/program.asm
+9
View File
@@ -0,0 +1,9 @@
_start:
addi x1, x0, 1
addi x2, x0, 4
sll x3, x1, x2
addi x4, x0, 31
sll x5, x1, x4
addi x6, x0, 0
sll x7, x1, x6
ebreak
tests/srl/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/srl/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/srl/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
ffffffff
00000004
0fffffff
0000001f
00000001
00000000
ffffffff
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/srl/program.asm
+9
View File
@@ -0,0 +1,9 @@
_start:
addi x1, x0, -1
addi x2, x0, 4
srl x3, x1, x2
addi x4, x0, 31
srl x5, x1, x4
addi x6, x0, 0
srl x7, x1, x6
ebreak
tests/sub/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/sub/expected_data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/sub/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
00000014
00000006
0000000e
fffffff2
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/sub/program.asm
+7
View File
@@ -0,0 +1,7 @@
_start:
addi x1, x0, 20
addi x2, x0, 6
sub x3, x1, x2
sub x4, x2, x1
sub x5, x1, x1
ebreak
tests/sw/data.hex
+1
View File
@@ -0,0 +1 @@
00000000
tests/sw/expected_data.hex
+3
View File
@@ -0,0 +1,3 @@
00000000
0000000a
00000063
tests/sw/expected_regs.hex
+32
View File
@@ -0,0 +1,32 @@
00000000
0000000a
00000014
00000063
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
tests/sw/program.asm
+8
View File
@@ -0,0 +1,8 @@
_start:
addi x1, x0, 10
addi x2, x0, 20
sw x1, 4(x0)
sw x2, 8(x0)
addi x3, x0, 99
sw x3, 8(x0)
ebreak