make testbench visible so simvision works

sim/behav/Include/cpu.include

@@ -7,7 +7,7 @@
 
 ../../src/verilog/cpu/cpu_top.sv
 ../../src/verilog/chip_top.sv
-../../src/verilog/tb_processor.svp
+../../src/verilog/tb_processor.sv
 
 // you MUST add any new files you make to this include file, follow the path naming above
 // aka '../../src/verilog/cpu/(your module here).sv'