make testbench visible so simvision works
This commit is contained in:
plittlefield6
@@ -7,7 +7,7 @@
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../../src/verilog/cpu/cpu_top.sv
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../../src/verilog/cpu/cpu_top.sv
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../../src/verilog/chip_top.sv
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../../src/verilog/chip_top.sv
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../../src/verilog/tb_processor.svp
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../../src/verilog/tb_processor.sv
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// you MUST add any new files you make to this include file, follow the path naming above
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// you MUST add any new files you make to this include file, follow the path naming above
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// aka '../../src/verilog/cpu/(your module here).sv'
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// aka '../../src/verilog/cpu/(your module here).sv'
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@@ -0,0 +1,287 @@
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`timescale 1ns/1ps
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module tb_processor;
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localparam time CLK_PERIOD = 20ns;
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localparam logic [13:0] ISRAM_BASE = 14'h0000;
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localparam logic [13:0] DSRAM_BASE = 14'h1000;
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localparam logic [13:0] REG_BASE = 14'h2000;
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localparam int ISRAM_WORDS = 1024;
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localparam int DSRAM_WORDS = 1024;
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localparam int REG_COUNT = 32;
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logic clk_i = 1'b0;
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logic rst_i;
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logic cpu_en_i;
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logic cpu_halt_o;
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logic halt_cpu;
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logic [13:0] addr;
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logic [31:0] wdata;
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logic w_en;
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logic r_en;
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logic [31:0] rdata;
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logic ready;
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logic [31:0] program_image [0:ISRAM_WORDS-1];
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logic [31:0] initial_data_image [0:DSRAM_WORDS-1]; //starting data for dsram
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logic [31:0] expected_data_image [0:DSRAM_WORDS-1]; //expected final dsram
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logic [31:0] expected_regs_image [0:REG_COUNT-1];
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string program_file;
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string data_file;
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string expected_data_file;
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string expected_regs_file;
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int program_words;
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int data_words;
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int expected_data_words;
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int max_cpu_cycles;
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int crossbar_timeout;
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int failures;
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always #(CLK_PERIOD / 2) clk_i = ~clk_i;
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chip_top dut (
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.clk_i (clk_i),
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.rst_i (rst_i),
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.en_cpu_i (cpu_en_i),
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.cpu_halted_o (cpu_halt_o),
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.halt_cpu_i (halt_cpu),
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.addr_i (addr),
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.wdata_i (wdata),
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.w_en_i (w_en),
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.r_en_i (r_en),
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.rdata_o (rdata),
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.rready_o (ready)
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);
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function automatic logic [13:0] word_address(
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input logic [13:0] base,
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input int unsigned word_index
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);
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word_address = base + (word_index << 2); //cleaning up byte offset
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endfunction
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task automatic crossbar_write(
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input logic [13:0] write_addr,
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input logic [31:0] write_data
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);
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int wait_cycles;
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begin
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if (write_addr[1:0] != 2'b00)
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$fatal(1, "Crossbar write address %h is not word-aligned",
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write_addr);
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@(negedge clk_i);
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addr <= write_addr;
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wdata <= write_data;
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w_en <= 1'b1;
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r_en <= 1'b0;
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@(negedge clk_i);
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w_en <= 1'b0;
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addr <= '0;
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wdata <= '0;
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end
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endtask
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task automatic crossbar_read(
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input logic [13:0] read_addr,
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output logic [31:0] read_data
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);
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int wait_cycles;
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begin
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if (read_addr[1:0] != 2'b00)
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$fatal(1, "Crossbar read address %h is not word-aligned",
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read_addr);
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@(negedge clk_i);
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addr <= read_addr;
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w_en <= 1'b0;
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r_en <= 1'b1;
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wait_cycles = 0;
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while (ready !== 1'b1) begin
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@(posedge clk_i);
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#1;
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wait_cycles++;
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if (wait_cycles >= crossbar_timeout)
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$fatal(1,
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"Crossbar read timed out at address %h",
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read_addr);
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end
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read_data = rdata;
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@(negedge clk_i);
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r_en <= 1'b0;
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addr <= '0;
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end
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endtask
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task automatic reset_dut;
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begin
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cpu_en_i <= 1'b0;
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rst_i <= 1'b1;
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repeat (3) @(posedge clk_i);
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@(negedge clk_i);
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rst_i <= 1'b0;
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end
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endtask
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task automatic load_program;
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int i;
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begin
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$display("Loading %0d instruction words from %s",
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program_words, program_file);
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$readmemh(program_file, program_image);
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for (i = 0; i < program_words; i++)
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crossbar_write(word_address(ISRAM_BASE, i),
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program_image[i]);
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end
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endtask
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task automatic load_initial_data;
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int i;
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begin
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if (data_words > 0) begin
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$display("Loading %0d data words from %s",
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data_words, data_file);
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$readmemh(data_file, initial_data_image);
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for (i = 0; i < data_words; i++)
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crossbar_write(word_address(DSRAM_BASE, i),
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initial_data_image[i]);
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end
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end
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endtask
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task automatic run_until_halt;
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int cycles;
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begin
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@(negedge clk_i);
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cpu_en_i <= 1'b1;
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cycles = 0;
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@(negedge clk_i);
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cpu_en_i <= 1'b0;
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while (cpu_halt_o !== 1'b1) begin
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@(posedge clk_i);
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#1;
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cycles++;
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if (cycles >= max_cpu_cycles)
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$fatal(1, "CPU did not halt within %0d cycles",
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max_cpu_cycles);
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end
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$display("CPU halted after %0d cycles", cycles);
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@(negedge clk_i);
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cpu_en_i <= 1'b0;
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repeat (3) @(negedge clk_i);
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end
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endtask
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task automatic check_word(
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input logic [13:0] check_addr,
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input logic [31:0] expected,
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input string description
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);
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logic [31:0] actual;
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begin
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crossbar_read(check_addr, actual);
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if (actual !== expected) begin
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failures++;
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$error("FAIL: %s at %h: expected %h, got %h",
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description, check_addr, expected, actual);
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end
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end
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endtask
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task automatic check_registers;
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int i;
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begin
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$readmemh(expected_regs_file, expected_regs_image);
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for (i = 0; i < REG_COUNT; i++)
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check_word(word_address(REG_BASE, i),
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expected_regs_image[i],
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$sformatf("register x%0d", i));
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end
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endtask
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task automatic check_data_memory;
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int i;
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begin
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if (expected_data_words > 0) begin
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$readmemh(expected_data_file, expected_data_image);
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for (i = 0; i < expected_data_words; i++)
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check_word(word_address(DSRAM_BASE, i),
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expected_data_image[i],
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$sformatf("data word %0d", i));
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end
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end
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endtask
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initial begin
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$shm_open("waves.shm");
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$shm_probe("AC");
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rst_i = 1'b1;
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cpu_en_i = 1'b0;
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halt_cpu = 1'b0;
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addr = '0;
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wdata = '0;
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w_en = 1'b0;
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r_en = 1'b0;
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failures = 0;
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program_words = 0;
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data_words = 0;
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expected_data_words = 0;
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max_cpu_cycles = 1000;
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crossbar_timeout = 20;
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if (!$value$plusargs("PROGRAM=%s", program_file))
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$fatal(1, "Missing required +PROGRAM=<program.hex> plusarg");
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if (!$value$plusargs("PROGRAM_WORDS=%d", program_words) ||
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program_words <= 0 || program_words > ISRAM_WORDS)
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$fatal(1, "PROGRAM_WORDS must be between 1 and %0d",
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ISRAM_WORDS);
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if ($value$plusargs("DATA=%s", data_file)) begin
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if (!$value$plusargs("DATA_WORDS=%d", data_words) ||
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data_words < 0 || data_words > DSRAM_WORDS)
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$fatal(1, "DATA_WORDS must be between 0 and %0d",
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DSRAM_WORDS);
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end
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if (!$value$plusargs("EXPECTED_REGS=%s", expected_regs_file))
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$fatal(1,
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"Missing required +EXPECTED_REGS=<expected_regs.hex> plusarg");
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if ($value$plusargs("EXPECTED_DATA=%s", expected_data_file)) begin
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if (!$value$plusargs("EXPECTED_DATA_WORDS=%d",
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expected_data_words) ||
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expected_data_words < 0 ||
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expected_data_words > DSRAM_WORDS)
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$fatal(1, "EXPECTED_DATA_WORDS must be between 0 and %0d",
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DSRAM_WORDS);
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end
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void'($value$plusargs("MAX_CPU_CYCLES=%d", max_cpu_cycles));
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void'($value$plusargs("CROSSBAR_TIMEOUT=%d", crossbar_timeout));
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reset_dut();
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load_program();
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load_initial_data();
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run_until_halt();
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check_registers();
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check_data_memory();
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if (failures == 0)
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$display("PASS: processor behavior matches expected results");
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else
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$fatal(1, "FAIL: processor test found %0d mismatch(es)",
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failures);
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$finish;
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end
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endmodule
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@@ -1,209 +0,0 @@
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//pragma protect begin_protected
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//pragma protect encrypt_agent="NCPROTECT"
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//pragma protect encrypt_agent_info="Encrypted using API"
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//pragma protect key_keyowner=Cadence Design Systems.
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//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2)
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//pragma protect key_method=RSA
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//pragma protect key_block
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AyB4/PdaKdcNPQnQ3SkT7E1YxNMdnVzwKFqaJL5r0UzLOm11Gy0Q+lg9ibUJsOar
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bv95EIiFSVLXgztIWsRlk/fcG9g1JYQo+kn1uMCv7/qrlfIhWSB3CaUU/RSBWNqk
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Eryj9VkWkAYvBPheECeTwbt6GTZQqqV9Fj46iH9hmAIvP5hB3aKd+khmEblM7Jp5
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YG8rXNFLgvagatedQ0aJWWL4M7ghm53Lb8oYbKPgrIKfBLC4vP4ZHE6RkJakKsT5
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Zehseo+GnnxZwtXKx/tODhCk2TrCwYH2UXlmKEkf7V1RtDit/u0KPhku7plv1vli
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IhFrnPc4OrY9I2nVchGY8w==
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//pragma protect end_key_block
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//pragma protect digest_block
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NFoMbWuzMDAJl2pWNb4BaFJV+ik=
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//pragma protect end_digest_block
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//pragma protect data_block
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LuTBsu1yk4iimn3N/I057jrUUW2T1hlgX6JUo6PRNtNSJGQkTXWGu5ayHj9LnewE
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ak2VW+UTASuam47Hb7BP6x6ue79GSwDMTtv06VtTUPg6/NoH1xC7N2WcubAGH2Hg
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||||||
DsvCs5P2QS+pzyz73B5UTxbSarpZgRJCCFoLUxY5wGORNm/QqMDNS43RWfYQ8xP8
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||||||
tlyzCRwL3hRcJMazM+vod25YJOA4X2mESsIyw8UGMpFyYkSW7HrCggt/bDZFX83A
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||||||
H50ubvmgmUEB0GsvVU8UlyGMPp0sm3f/LNIG3wgA4ge9CDioK+BXrW1McOS2OWPA
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||||||
KIKisCuq9EtJaoHGVJoAiwLudac59J20pLgnpF86Wj5Ic1DkiVt0huKOriu0XiDj
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||||||
/tbB7SSQJfhYBB/eW1ZIiGf/qne/Fb5KAthwdQRPG8oLfn5AQdjwWiAaWtp7qi/b
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||||||
AEGPAmB8YJOCaaX/ARz9f9H8tu4Ey87+Tq24dXruL+prvLcfSvsUNsf7MP9tl7Je
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||||||
n4QGTFrll2VkPtAkJqDPFQo481sY3NEjz114xFwzmGC45FnaV1kcmuokvnmfSdSV
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||||||
5edFCWAYb5P2zG8zXwmZcdtp7qQ6yQ0/Q7VfQVeX285Qxxz6+JWz4cTOBJp69ugK
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||||||
dUYz2fOa2QX2wM35vC7LHNaVgFIuKrDaceIckW5BQTpXqvlPqKd0WAXThb8QKMjs
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||||||
kWebFYVbqV3shlTgAYivQTOZ1twStuLI1wPPsLuHZsupRraDqRK9C+pEETg3PYG0
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||||||
Po9VEsZJx+XBm1di+FbVgXmkOjuxGEKk8bw+fOSlmqtvzVTrY+D1qKDNfskoBst8
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||||||
svmEnHRTr0LFlTE+USe1mPpEQQeebDzzwl7kD1SqpaiAQ/yD92+oNaQznMIJeX2T
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||||||
LSamAB3foV3rBkfWWa3urYUrBv279/kL2O8ETdbivxTbpdeesQj5sthQYy5ifT4i
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||||||
twxQdngzeHHsrraWJWRMdzXzWtFKroMI3IUMwcgWxpP96/9idzx1/ZPpvvsTh7/J
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||||||
VaebTnnEIpsg9/AkQCj/H7LTiS/yMNzKFD+1JCk1lWL1pPU6zAFGW3/XZjR2jDPW
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PRt1Gw4fNeVn4koW3+kZjosj5MV/voh6NaUTjS34NG0m+9hshg6Bp+5Q4tyt0A/z
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||||||
LpDnOb9IYhEUNRJrixBch5jTjl8QCbpLxFk6M5C+Hu4IKzxPA8hWJAN/6/GuEsfW
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||||||
H2fypTx6KmGjyA+4kWflAK1DRIKeQ/vhaVWYRFH2gEIGtrUsBe0Hd2IaBmKM02Dj
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||||||
C9e3L5l5v41iNmdBoytgiQ4uUcUl1v0gj7FtSkx5QnTNb0nRsxaYTHJRbgLOeiV7
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||||||
vKMyEuJneqdIZmK2BCbRz3+XaPEW+dlrzE1Oi5dRWm2XYqZyQsP4e561QhUztS7t
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|
||||||
j313XVRtREqw7f0kFOMCc0PtM5j/0Jl8Th7hdaCGnQCiB7VwlefNuRXKJCPWBcjx
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G1zxYOP8KzvzTartC9178DwBGjzqzDMXce1b3iJVYyS2vapB3dpHlbK6KVAuchlS
|
|
||||||
avCS9Apm8okkgghm4TbccPuG4oP5mKMNS/udOnHRUxD/Fe2v///N1cbu8DfNr6jV
|
|
||||||
tl8XUih3OckCD2MCKXjQsW3zeaIgLRHiGYgzubPYTEchOA8BxlynohwrNCPzpR7y
|
|
||||||
glEZ2+Quj5fkOdkCr7wwcnoLgDWw50q6Pii++wrpwsJKFxArI8lOWvzXdVQzIU5h
|
|
||||||
d6wJLVETghDep/l2TCEx3vOhszRo9c5LvdFkOoIIVeuBelF5anmmLV10e6OdAiKZ
|
|
||||||
gbH7FEG1DB6+hxCRItDUUoYXgz0/sekEL+qnq1p4IhFHYE/j1rKaBdpYNGmddkUE
|
|
||||||
8HtG7nY6bz1xZsdjDOc+EdgOK+D1kx9u3sRrALM2BKtPSWY/UfmoBxWQMzmrR/GF
|
|
||||||
bU5rAzQU7L68VOEy9XhlRKHNutw47KXcwGjUSbz89HC9NNWVnMmIZGHmTU+01i8V
|
|
||||||
TG4BnuURzz+ZL2PBYds3mYOhZc2L/VrgqEutkdz7ycA7NJEUuf1AOKosLhAyEexA
|
|
||||||
dfymwly3m+1ll1sy2mKrHcAc007i0y9klQ/XbtvcBXK6PQIuZQY0OsKOJgmBjTcY
|
|
||||||
x14xqrPvXrU9a5G6UwPlApddeYuCndJaooOSK5DIbGssOQSbvYtOHp9v244PBXQ4
|
|
||||||
dCfXovFRb2j1dKnxJntBuYj3YgPPPb62SChstVhYZUycC+uv9qxk+rcGB0R/T7DQ
|
|
||||||
jdou+JJthlOiw873yAYjQxZf8MLMLXoUcSQ5wlgKEh5MXdEJLXSmCkH1/wuuPGbN
|
|
||||||
Wo1o9BLEzm6QMFQGfSKedFBeys91DPt6GiR88pieO+2xTYOK9ORjPoRfqmah5VoD
|
|
||||||
rHtrwj6KkD2ynv0XKP/QLeFnTueizti6dd3soBr6VJpOarAyru+fDefGtbHaeeJh
|
|
||||||
dE5ZlPOS3Z9ToNPu6tDlRtPuxYGD8m25jmkJ+Z7vDMkZBk0Q+Lig++EK25T/sdsP
|
|
||||||
yO0sicXIslNNMjM1z/0+qYdrRJQARR+yK5XJar4VUOBb+EmXywxqfBTBkshs7/ZV
|
|
||||||
Uqw52szzvaqqOg6/BskViPTHvylG1GpQTZblsyB9s5RwOeGVxWK/yDWDsWzxpH3w
|
|
||||||
kcD/DPCBHt3+mwPPYeu4qaEDGoExLK0AiTjsMJhnFfhZsUi++UVF90vGs8Pnz44P
|
|
||||||
8WC2FdiYQb6OiH4zZxge2K7/jL1WTXeHqApkFScnd76Nawv0WcEa+gFzJjjNE7oQ
|
|
||||||
DHyobudY12EyhcvwMfeCLaB0lPQLKv1hL+J62m4XBi3pI8oGjgbmR5x6kf+zgD+D
|
|
||||||
4EeXkBRj/ALZoddCNyCPPGumn0biNqEkPoczhFQ+sxc9+BUVKrdpWX9eMVGuKkD3
|
|
||||||
CwsNoDwb0ejgkrjrLYJU6wT8VUt9Fpxz7zSYKO3D0ntImcIHU+lx6uhR9mO9ivC3
|
|
||||||
06vqawXBF6I2L36LNvNkyvhgne1MPvvylEpJBOHjBfwCcKtOx0u2ErYFufnuEm96
|
|
||||||
9rRdiNYTVupIKrL4WUpD2eUODEVNcS8+FQG4tmseabPCM4IViqpoX+dNHltQsf+p
|
|
||||||
YNflnBNrEjludQ7ylmJf00QNbjl3qqgbPwkRTCRzwtSWNO2sXkURW6W+9J/Se/hx
|
|
||||||
yJsaNHSvJsMt6IyDsTLB0cOx/iD3oZre5SvdlcCYI3474J+T7M5w14uDvT2jx6yc
|
|
||||||
EiVUzzFUiyP4tXOb9/OKMz8Y69L5+HdlsKJ8u2ttH6yYqX8dadBvRNAKIWv2Rwh0
|
|
||||||
Ybo6c+R+McMkrk6kpNNA/IgNjInapP/N0zZRivq7IoNmzxJuIFYXhvU1LR5ZyMF3
|
|
||||||
1eo1NFESgRuzbbFuXvqUge6b1YEdeIN3gstH7VTBnHuA/DMModfUgwARtlS+S4AC
|
|
||||||
//pragma protect end_data_block
|
|
||||||
//pragma protect digest_block
|
|
||||||
n/HPYx0H7ZW2nhgXuEVMBJXzP0Q=
|
|
||||||
//pragma protect end_digest_block
|
|
||||||
//pragma protect end_protected
|
|
||||||
Reference in New Issue
Block a user