diff --git a/Makefile b/Makefile
index b4082cf..052ffbb 100644
--- a/Makefile
+++ b/Makefile
@@ -80,7 +80,6 @@ submit:
 	if [ $$status -ne 0 ]; then echo "WARNING: not all tests pass, see regress.log"; fi; \
 	echo "Wrote $$submission"
 
->>>>>>> upstream/main
 clean:
 	$(MAKE) -C sim/behav clean
 	$(MAKE) --no-print-directory clean-generated
diff --git a/src/verilog/cpu/cpu_top.sv b/src/verilog/cpu/cpu_top.sv
index 6b43435..edba9bf 100644
--- a/src/verilog/cpu/cpu_top.sv
+++ b/src/verilog/cpu/cpu_top.sv
@@ -5,7 +5,6 @@
 // END SYSTEM HEADER
 
 module cpu_top (
-<<<<<<< HEAD
     input logic clk_i,
     input logic rst_i,
     input logic en_i,