From 55a0856b5f9a1b5e1486aacd661ebbe1552d3c2c Mon Sep 17 00:00:00 2001
From: Benzi <dbenzi3@ece-rhelsrv.ece.gatech.edu>
Date: Sun, 20 Sep 2026 19:32:01 -0400
Subject: [PATCH] remove conflict scaffolding

---
 Makefile                   | 1 -
 src/verilog/cpu/cpu_top.sv | 1 -
 2 files changed, 2 deletions(-)

diff --git a/Makefile b/Makefile
index b4082cf..052ffbb 100644
--- a/Makefile
+++ b/Makefile
@@ -80,7 +80,6 @@ submit:
 	if [ $$status -ne 0 ]; then echo "WARNING: not all tests pass, see regress.log"; fi; \
 	echo "Wrote $$submission"
 
->>>>>>> upstream/main
 clean:
 	$(MAKE) -C sim/behav clean
 	$(MAKE) --no-print-directory clean-generated
diff --git a/src/verilog/cpu/cpu_top.sv b/src/verilog/cpu/cpu_top.sv
index 6b43435..edba9bf 100644
--- a/src/verilog/cpu/cpu_top.sv
+++ b/src/verilog/cpu/cpu_top.sv
@@ -5,7 +5,6 @@
 // END SYSTEM HEADER
 
 module cpu_top (
-<<<<<<< HEAD
     input logic clk_i,
     input logic rst_i,
     input logic en_i,