From 5856ab3d7c8076eed270fe7339ca4b5cededdc54 Mon Sep 17 00:00:00 2001
From: dylanbenzi <dylanbenzi@gmail.com>
Date: Sun, 20 Sep 2026 18:33:39 -0400
Subject: [PATCH] fix load stall declaration

---
 src/verilog/cpu/control_unit.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/verilog/cpu/control_unit.sv b/src/verilog/cpu/control_unit.sv
index 5333804..68319f6 100644
--- a/src/verilog/cpu/control_unit.sv
+++ b/src/verilog/cpu/control_unit.sv
@@ -21,7 +21,7 @@ module main_decoder (
     mem_write_o = 1'b0;
     alu_src_o = 1'b0;
     alu_op_o = 1'b00;
-    load_stall = 1'b0;
+    load_stall_o = 1'b0;
 
     case (opcode_i)
       // lw
@@ -33,7 +33,7 @@ module main_decoder (
         result_src_o = 1'b1;
         branch_o = 1'b0;
         alu_op_o = 2'b00;
-        load_stall = 1'b1;
+        load_stall_o = 1'b1;
       end
       // sw
       7'b0100011: begin