fix alu result output

src/verilog/cpu/execute.sv

@@ -6,24 +6,21 @@ module alu (
     output logic alu_zero_o,
     output logic [31:0] alu_result_o
 );
-
-  logic [31:0] result;
-
   always_comb begin
     unique case (alu_control_i)
       // add
-      2'b00: result = a_i + b_i;
+      2'b00: alu_result_o = a_i + b_i;
       // sub
-      2'b01: result = a_i - b_i;
+      2'b01: alu_result_o = a_i - b_i;
       // sll
       // can only shift by 32 pos
-      2'b10: result = a_i << b_i[4:0];
+      2'b10: alu_result_o = a_i << b_i[4:0];
       // srl
       // can only shift by 32 pos
-      2'b11: result = a_i >> b_i[4:0];
+      2'b11: alu_result_o = a_i >> b_i[4:0];
     endcase
 
-    alu_zero_o = (result == 1'b0);
+    alu_zero_o = (alu_result_o == 1'b0);
   end
 endmodule