From 729c0dfdc329e09ef0ca44acd2bd4ebfd4c5c172 Mon Sep 17 00:00:00 2001 From: dylanbenzi Date: Sun, 20 Sep 2026 17:47:04 -0400 Subject: [PATCH] fix instr invld bug --- src/verilog/cpu/control_unit.sv | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/verilog/cpu/control_unit.sv b/src/verilog/cpu/control_unit.sv index 530e2bf..dfb18ed 100644 --- a/src/verilog/cpu/control_unit.sv +++ b/src/verilog/cpu/control_unit.sv @@ -150,14 +150,18 @@ module control_unit ( output logic ebreak_o ); - logic [6:0] opcode = instr_i[6:0]; - logic [2:0] funct3 = instr_i[14:12]; - logic funct7 = instr_i[30]; + logic [6:0] opcode; + logic [2:0] funct3; + logic funct7; logic [1:0] alu_op; logic instr_invld_md; logic instr_invld_ad; logic branch_o; + assign opcode = instr_i[6:0]; + assign funct3 = instr_i[14:12]; + assign funct7 = instr_i[30]; + assign ebreak_o = (opcode == 7'b1110011) && (funct3 == 3'b000) && (instr_i[31:20] == 12'h1); main_decoder md (