initial module setup and declaration

src/verilog/cpu/cpu_top.sv

@@ -61,6 +61,17 @@ module cpu_top (
       .branch_taken_i(branch_taken)
   );
 
+  logic alu_zero;
+  logic result_src;
+  logic mem_write;
+  logic alu_src;
+  logic [1:0] alu_control;
+  logic [31:0] imm_ext;
+  logic [31:0] rs1_data;
+  logic [31:0] rs2_data;
+  logic instr_invld_decode;
+  logic [31:0] alu_result;
+
   //tied off, do fix
   assign branch_vld = 1'b0;
   assign branch_trgt = '0;
@@ -80,9 +91,47 @@ module cpu_top (
 
   // Disconnect this once you instantiate reg_file and connect reg_file's output to it instead
   //assign reg_crossbar_o = '{default: '0};
-  assign reg_crossbar_o = registers;
 
+  initial begin
+    for (int i = 0; i < 32; i++) begin
+      reg_crossbar_o[i] = reg_values_o[i];
+    end
+  end
 
 
   // instantiate the other modules you make here//
+  decode decode (
+      .clk_i(clk_i),
+      .rst_i(rst_i),
+      .instr_i(instr),
+      .instr_vld_i(instr_vld),
+      .alu_zero_i(alu_zero),
+      .rd_data_i(result),
+      .pc_src_o(),
+      .result_src_o(result_src),
+      .mem_write_o(dsram_write_en_o),
+      .alu_src_o(alu_src),
+      .alu_control_o(alu_control),
+      .imm_ext_o(imm_ext),
+      .rs1_data_o(rs1_data),
+      .rs2_data_o(rs2_data),
+      .instr_invld_o(instr_invld_decode)
+  );
+
+  execute execute (
+      .clk_i(clk_i),
+      .alu_src_i(alu_src),
+      .imm_ext_i(imm_ext),
+      .alu_control_i(alu_control),
+      .current_pc_i(current_pc),
+      .rs1_data_i(rs1_data),
+      .rs2_data_i(rs2_data),
+      .alu_zero_o(alu_zero),
+      .alu_result_o(alu_result),
+      .pc_target_o()
+  );
+
+  assign dsram_addr_o = alu_result[9:0];
+  logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
+
 endmodule