initial module setup and declaration

src/verilog/cpu/decode.sv

@@ -0,0 +1,59 @@
+module decode (
+    input logic clk_i,
+    input logic rst_i,
+    input logic [31:0] instr_i,  // instruction to decode
+    input logic instr_vld_i,  // is instruction passed valid
+    input logic alu_zero_i,
+    input logic [31:0] rd_data_i,
+
+    output logic pc_src_o,
+    output logic result_src_o,
+    output logic mem_write_o,
+    output logic alu_src_o,
+    output logic [1:0] alu_control_o,
+    output logic [31:0] imm_ext_o,
+    output logic [31:0] rs1_data_o,
+    output logic [31:0] rs2_data_o,
+    output logic instr_invld_o
+);
+
+  logic [1:0] imm_src;
+  logic reg_write;
+  logic cu_invld;
+  logic se_invld;
+
+  assign instr_invld_o = ~instr_vld_i | cu_invld | se_invld; // instruction is invalid if provided invalid or decoded invalid
+
+  control_unit cu (
+      .instr_i(instr_i),
+      .zero_flag_i(alu_zero_i),
+      .pc_src_o(pc_src_o),
+      .result_src_o(result_src_o),
+      .mem_write_o(mem_write_o),
+      .alu_src_o(alu_src_o),
+      .imm_src_o(imm_src),
+      .reg_write_o(reg_write),
+      .alu_control_o(alu_control_o),
+      .instr_invld_o(cu_invld)
+  );
+
+  reg_file rf (
+      .clk_i(clk_i),
+      .rst_i(rst_i),
+      .rs1_addr_i(instr_i[19:15]),
+      .rs2_addr_i(instr_i[24:20]),
+      .rs1_data_o(rs1_data_o),
+      .rs2_data_o(rs2_data_o),
+      .rd_write_en_i(reg_write),
+      .rd_addr_i(instr_i[11:7]),
+      .rd_data_i(rd_data_i)
+  );
+
+  sign_extend se (
+      .instr_i(instr_i),
+      .imm_src_i(imm_src),
+      .imm_ext_o(imm_ext_o),
+      .instr_invld_o(se_invld)
+  );
+
+endmodule