From 88d09745858521d5214cfc6d2325e570970f91f0 Mon Sep 17 00:00:00 2001
From: dylanbenzi <dylanbenzi@gmail.com>
Date: Sun, 20 Sep 2026 17:51:44 -0400
Subject: [PATCH] fix logic assign bugs

---
 src/verilog/cpu/cpu_top.sv | 3 ++-
 src/verilog/cpu/execute.sv | 6 ++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/verilog/cpu/cpu_top.sv b/src/verilog/cpu/cpu_top.sv
index a7d1080..356bc44 100644
--- a/src/verilog/cpu/cpu_top.sv
+++ b/src/verilog/cpu/cpu_top.sv
@@ -54,7 +54,8 @@ module cpu_top (
   logic [9:0] branch_trgt;
   logic branch_taken;
 
-  logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
+  logic [31:0] result;
+  assign result = result_src ? dsram_rdata_i : alu_result;
 
   logic ebreak_latch;
 
diff --git a/src/verilog/cpu/execute.sv b/src/verilog/cpu/execute.sv
index d525829..5d68dd6 100644
--- a/src/verilog/cpu/execute.sv
+++ b/src/verilog/cpu/execute.sv
@@ -41,9 +41,11 @@ module execute (
     output logic [31:0] pc_target_o
 );
 
-  logic [31:0] a = rs1_data_i;
-  logic [31:0] b = alu_src_i ? imm_ext_i : rs2_data_i;
+  logic [31:0] a;
+  logic [31:0] b;
 
+  assign a = rs1_data_i;
+  assign b = alu_src_i ? imm_ext_i : rs2_data_i;
   assign pc_target_o = current_pc_i + imm_ext_i;
 
   alu alu (