diff --git a/src/verilog/cpu/control_unit.sv b/src/verilog/cpu/control_unit.sv
index dfb18ed..5333804 100644
--- a/src/verilog/cpu/control_unit.sv
+++ b/src/verilog/cpu/control_unit.sv
@@ -8,6 +8,7 @@ module main_decoder (
     output logic [1:0] imm_src_o,  //
     output logic reg_write_o,  // write to register or not
     output logic [1:0] alu_op_o,  // operation for alu to perform
+    output logic load_stall_o,
     output logic instr_invld_o  // invalid or unsupported instruction
 );
 
@@ -20,6 +21,7 @@ module main_decoder (
     mem_write_o = 1'b0;
     alu_src_o = 1'b0;
     alu_op_o = 1'b00;
+    load_stall = 1'b0;
 
     case (opcode_i)
       // lw
@@ -31,6 +33,7 @@ module main_decoder (
         result_src_o = 1'b1;
         branch_o = 1'b0;
         alu_op_o = 2'b00;
+        load_stall = 1'b1;
       end
       // sw
       7'b0100011: begin
@@ -146,6 +149,7 @@ module control_unit (
     output logic [1:0] imm_src_o,
     output logic reg_write_o,
     output logic [1:0] alu_control_o,
+    output logic load_stall_o,
     output logic instr_invld_o,
     output logic ebreak_o
 );
@@ -173,7 +177,8 @@ module control_unit (
       .reg_write_o(reg_write_o),
       .mem_write_o(mem_write_o),
       .alu_op_o(alu_op),
-      .instr_invld_o(instr_invld_md)
+      .instr_invld_o(instr_invld_md),
+      .load_stall_o(load_stall_o)
   );
 
   alu_decoder ad (
diff --git a/src/verilog/cpu/cpu_top.sv b/src/verilog/cpu/cpu_top.sv
index 356bc44..2003964 100644
--- a/src/verilog/cpu/cpu_top.sv
+++ b/src/verilog/cpu/cpu_top.sv
@@ -58,8 +58,9 @@ module cpu_top (
   assign result = result_src ? dsram_rdata_i : alu_result;
 
   logic ebreak_latch;
+  logic load_stall;
 
-  assign stall_core = ebreak_latch | halted_o | ~en_i;  //when else would you stall?
+  assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall;  //when else would you stall?
 
   // === Instruction Fetch === //
   // certain ports are tied off bc they depend on modulees you need to implement.
@@ -99,6 +100,7 @@ module cpu_top (
       .imm_ext_o(imm_ext),
       .rs1_data_o(rs1_data),
       .rs2_data_o(rs2_data),
+      .load_stall_o(load_stall),
       .instr_invld_o(instr_invld_decode),
       .reg_values_o(reg_crossbar_o),
       .ebreak_o(ebreak_latch)
diff --git a/src/verilog/cpu/decode.sv b/src/verilog/cpu/decode.sv
index 3822bf4..7cc2b76 100644
--- a/src/verilog/cpu/decode.sv
+++ b/src/verilog/cpu/decode.sv
@@ -14,6 +14,7 @@ module decode (
     output logic [31:0] imm_ext_o,
     output logic [31:0] rs1_data_o,
     output logic [31:0] rs2_data_o,
+    output logic load_stall_o,
     output logic instr_invld_o,
     output logic ebreak_o,
     output logic [31:0] reg_values_o[32]  //Register Values Output
@@ -36,6 +37,7 @@ module decode (
       .imm_src_o(imm_src),
       .reg_write_o(reg_write),
       .alu_control_o(alu_control_o),
+      .load_stall_o(load_stall_o),
       .instr_invld_o(cu_invld),
       .ebreak_o(ebreak_o)
   );