update all modules

src/verilog/cpu/cpu_top.sv

@@ -36,9 +36,6 @@ module cpu_top (
   logic [31:0] instr;
   logic [31:0] current_pc;
   logic instr_vld;
-  logic branch_vld;
-  logic [9:0] branch_trgt;
-  logic branch_taken;
 
   assign stall_core = halted_o | ~en_i;  //when else would you stall?
 
@@ -72,34 +69,10 @@ module cpu_top (
   logic instr_invld_decode;
   logic [31:0] alu_result;
 
-  //tied off, do fix
-  assign branch_vld = 1'b0;
-  assign branch_trgt = '0;
-  assign branch_taken = 1'b0;
 
-  // Unused outputs tied off until downstream modules are added
-  assign halted_o = 1'b0; //what instr should halt the cpu? does this make sense to be combinational or sequential?
+  assign dsram_en_o = 1'b1;
+  assign dsram_wdata_o = rs2_data;
 
-  assign dsram_en_o = 1'b0;
-  assign dsram_write_en_o = 1'b0;
-  assign dsram_addr_o = '0;
-  assign dsram_wdata_o = '0;
-
-
-
-  // TODO: DO THIS FIRST, instantiate our Register File//
-
-  // Disconnect this once you instantiate reg_file and connect reg_file's output to it instead
-  //assign reg_crossbar_o = '{default: '0};
-
-  initial begin
-    for (int i = 0; i < 32; i++) begin
-      reg_crossbar_o[i] = reg_values_o[i];
-    end
-  end
-
-
-  // instantiate the other modules you make here//
   decode decode (
       .clk_i(clk_i),
       .rst_i(rst_i),
@@ -107,7 +80,7 @@ module cpu_top (
       .instr_vld_i(instr_vld),
       .alu_zero_i(alu_zero),
       .rd_data_i(result),
-      .pc_src_o(),
+      .pc_src_o(branch_taken),
       .result_src_o(result_src),
       .mem_write_o(dsram_write_en_o),
       .alu_src_o(alu_src),
@@ -115,9 +88,27 @@ module cpu_top (
       .imm_ext_o(imm_ext),
       .rs1_data_o(rs1_data),
       .rs2_data_o(rs2_data),
-      .instr_invld_o(instr_invld_decode)
+      .instr_invld_o(instr_invld_decode),
+      .reg_values_o(reg_crossbar_o),
+      .ebreak_o(halted_o)
   );
 
+  logic [31:0] pc_target;
+
+  logic branch_vld;
+  logic [9:0] branch_trgt;
+  logic branch_taken;
+
+  always_comb begin
+    if (pc_target[31:12] == '0) begin
+      branch_vld  = '1;
+      branch_trgt = pc_target[11:2];
+    end else begin
+      branch_vld  = '0;
+      branch_trgt = '0;
+    end
+  end
+
   execute execute (
       .clk_i(clk_i),
       .alu_src_i(alu_src),
@@ -128,10 +119,10 @@ module cpu_top (
       .rs2_data_i(rs2_data),
       .alu_zero_o(alu_zero),
       .alu_result_o(alu_result),
-      .pc_target_o()
+      .pc_target_o(pc_target)
   );
 
-  assign dsram_addr_o = alu_result[9:0];
+  assign dsram_addr_o = alu_result[11:2];
   logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
 
 endmodule