update all modules

src/verilog/cpu/decode.sv

@@ -14,7 +14,9 @@ module decode (
     output logic [31:0] imm_ext_o,
     output logic [31:0] rs1_data_o,
     output logic [31:0] rs2_data_o,
-    output logic instr_invld_o
+    output logic instr_invld_o,
+    output logic ebreak_o,
+    output logic [31:0] reg_values_o[32]  //Register Values Output
 );
 
   logic [1:0] imm_src;
@@ -34,7 +36,8 @@ module decode (
       .imm_src_o(imm_src),
       .reg_write_o(reg_write),
       .alu_control_o(alu_control_o),
-      .instr_invld_o(cu_invld)
+      .instr_invld_o(cu_invld),
+      .ebreak_o(ebreak_o)
   );
 
   reg_file rf (
@@ -46,7 +49,8 @@ module decode (
       .rs2_data_o(rs2_data_o),
       .rd_write_en_i(reg_write),
       .rd_addr_i(instr_i[11:7]),
-      .rd_data_i(rd_data_i)
+      .rd_data_i(rd_data_i),
+      .reg_values_o(reg_values_o)
   );
 
   sign_extend se (