update all modules

src/verilog/cpu/execute.sv

@@ -12,16 +12,18 @@ module alu (
   always_comb begin
     unique case (alu_control_i)
       // add
-      2'b00: result = a + b;
+      2'b00: result = a_i + b_i;
       // sub
-      2'b01: result = a - b;
+      2'b01: result = a_i - b_i;
       // sll
-      2'b10: result = a << b;
+      // can only shift by 32 pos
+      2'b10: result = a_i << b_i[4:0];
       // srl
-      2'b11: result = a >> b;
+      // can only shift by 32 pos
+      2'b11: result = a_i >> b_i[4:0];
     endcase
 
-    assign alu_zero_o = (result == 1'b0);
+    alu_zero_o = (result == 1'b0);
   end
 endmodule
 
@@ -39,8 +41,8 @@ module execute (
     output logic [31:0] pc_target_o
 );
 
-  logic [31:0] a = rs1_data;
-  logic [31:0] b = alu_src_i ? imm_ext_i : rs2_data;
+  logic [31:0] a = rs1_data_i;
+  logic [31:0] b = alu_src_i ? imm_ext_i : rs2_data_i;
 
   assign pc_target_o = current_pc_i + imm_ext_i;