update all modules

src/verilog/cpu/control_unit.sv

@@ -12,6 +12,15 @@ module main_decoder (
 );
 
   always_comb begin
+    imm_src_o = 1'b0;
+    result_src_o = 1'b0;
+    instr_invld_o = 1'b0;
+    reg_write_o = 1'b0;
+    branch_o = 1'b0;
+    mem_write_o = 1'b0;
+    alu_src_o = 1'b0;
+    alu_op_o = 1'b00;
+
     case (opcode_i)
       // lw
       7'b0000011: begin
@@ -41,8 +50,18 @@ module main_decoder (
         branch_o = 1'b0;
         alu_op_o = 2'b10;
       end
+      // addi
+      7'b0010011: begin
+        reg_write_o = 1'b1;
+        imm_src_o = 2'b00;
+        alu_src_o = 1'b1;
+        mem_write_o = 1'b0;
+        result_src_o = 1'b0;
+        branch_o = 1'b0;
+        alu_op_o = 2'b10;
+      end
       // beq
-      7'b0110011: begin
+      7'b1100011: begin
         reg_write_o = 1'b0;
         imm_src_o = 2'b10;
         alu_src_o = 1'b0;
@@ -50,6 +69,16 @@ module main_decoder (
         branch_o = 1'b1;
         alu_op_o = 2'b01;
       end
+      // ebreak
+      7'b1110011: begin
+        reg_write_o = 1'b0;
+        imm_src_o = 2'b00;
+        alu_src_o = 1'b1;
+        mem_write_o = 1'b0;
+        result_src_o = 1'b0;
+        branch_o = 1'b0;
+        alu_op_o = 2'b00;
+      end
       // invalid or unsupported instruction
       default: instr_invld_o = 1'b1;
     endcase
@@ -68,12 +97,14 @@ module alu_decoder (
 );
 
   always_comb begin
+    instr_invld_o = 1'b0;
+    alu_control_o = 1'b00;
     case (alu_op_i)
       // lw, sw (alu add)
       2'b00:   alu_control_o = 2'b00;
       // beq (alu sub)
       2'b01:   alu_control_o = 2'b01;
-      // R type
+      // R type or addi
       2'b10: begin
         case (funct3_i)
           // add, sub
@@ -89,11 +120,11 @@ module alu_decoder (
           end
           // sll
           3'b001: begin
-            alu_control = 2'b10;
+            alu_control_o = 2'b10;
           end
           // srl
           3'b101: begin
-            alu_control = 2'b11;
+            alu_control_o = 2'b11;
           end
           default: instr_invld_o = 1'b1;
         endcase
@@ -115,7 +146,8 @@ module control_unit (
     output logic [1:0] imm_src_o,
     output logic reg_write_o,
     output logic [1:0] alu_control_o,
-    output logic instr_invld_o
+    output logic instr_invld_o,
+    output logic ebreak_o
 );
 
   logic [6:0] opcode = instr_i[6:0];
@@ -124,6 +156,9 @@ module control_unit (
   logic [1:0] alu_op;
   logic instr_invld_md;
   logic instr_invld_ad;
+  logic branch_o;
+
+  assign ebreak_o = (opcode == 7'b1110011) && (funct3 == 3'b000) && (instr_i[31:20] == 12'h1);
 
   main_decoder md (
       .opcode_i(opcode),

src/verilog/cpu/cpu_top.sv

@@ -36,9 +36,6 @@ module cpu_top (
   logic [31:0] instr;
   logic [31:0] current_pc;
   logic instr_vld;
-  logic branch_vld;
-  logic [9:0] branch_trgt;
-  logic branch_taken;
 
   assign stall_core = halted_o | ~en_i;  //when else would you stall?
 
@@ -72,34 +69,10 @@ module cpu_top (
   logic instr_invld_decode;
   logic [31:0] alu_result;
 
-  //tied off, do fix
-  assign branch_vld = 1'b0;
-  assign branch_trgt = '0;
-  assign branch_taken = 1'b0;
 
-  // Unused outputs tied off until downstream modules are added
+  assign dsram_en_o = 1'b1;
-  assign halted_o = 1'b0; //what instr should halt the cpu? does this make sense to be combinational or sequential?
+  assign dsram_wdata_o = rs2_data;
 
-  assign dsram_en_o = 1'b0;
-  assign dsram_write_en_o = 1'b0;
-  assign dsram_addr_o = '0;
-  assign dsram_wdata_o = '0;
-
-
-
-  // TODO: DO THIS FIRST, instantiate our Register File//
-
-  // Disconnect this once you instantiate reg_file and connect reg_file's output to it instead
-  //assign reg_crossbar_o = '{default: '0};
-
-  initial begin
-    for (int i = 0; i < 32; i++) begin
-      reg_crossbar_o[i] = reg_values_o[i];
-    end
-  end
-
-
-  // instantiate the other modules you make here//
   decode decode (
       .clk_i(clk_i),
       .rst_i(rst_i),
@@ -107,7 +80,7 @@ module cpu_top (
       .instr_vld_i(instr_vld),
       .alu_zero_i(alu_zero),
       .rd_data_i(result),
-      .pc_src_o(),
+      .pc_src_o(branch_taken),
       .result_src_o(result_src),
       .mem_write_o(dsram_write_en_o),
       .alu_src_o(alu_src),
@@ -115,9 +88,27 @@ module cpu_top (
       .imm_ext_o(imm_ext),
       .rs1_data_o(rs1_data),
       .rs2_data_o(rs2_data),
-      .instr_invld_o(instr_invld_decode)
+      .instr_invld_o(instr_invld_decode),
+      .reg_values_o(reg_crossbar_o),
+      .ebreak_o(halted_o)
   );
 
+  logic [31:0] pc_target;
+
+  logic branch_vld;
+  logic [9:0] branch_trgt;
+  logic branch_taken;
+
+  always_comb begin
+    if (pc_target[31:12] == '0) begin
+      branch_vld  = '1;
+      branch_trgt = pc_target[11:2];
+    end else begin
+      branch_vld  = '0;
+      branch_trgt = '0;
+    end
+  end
+
   execute execute (
       .clk_i(clk_i),
       .alu_src_i(alu_src),
@@ -128,10 +119,10 @@ module cpu_top (
       .rs2_data_i(rs2_data),
       .alu_zero_o(alu_zero),
       .alu_result_o(alu_result),
-      .pc_target_o()
+      .pc_target_o(pc_target)
   );
 
-  assign dsram_addr_o = alu_result[9:0];
+  assign dsram_addr_o = alu_result[11:2];
   logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
 
 endmodule

src/verilog/cpu/decode.sv

@@ -14,7 +14,9 @@ module decode (
     output logic [31:0] imm_ext_o,
     output logic [31:0] rs1_data_o,
     output logic [31:0] rs2_data_o,
-    output logic instr_invld_o
+    output logic instr_invld_o,
+    output logic ebreak_o,
+    output logic [31:0] reg_values_o[32]  //Register Values Output
 );
 
   logic [1:0] imm_src;
@@ -34,7 +36,8 @@ module decode (
       .imm_src_o(imm_src),
       .reg_write_o(reg_write),
       .alu_control_o(alu_control_o),
-      .instr_invld_o(cu_invld)
+      .instr_invld_o(cu_invld),
+      .ebreak_o(ebreak_o)
   );
 
   reg_file rf (
@@ -46,7 +49,8 @@ module decode (
       .rs2_data_o(rs2_data_o),
       .rd_write_en_i(reg_write),
       .rd_addr_i(instr_i[11:7]),
-      .rd_data_i(rd_data_i)
+      .rd_data_i(rd_data_i),
+      .reg_values_o(reg_values_o)
   );
 
   sign_extend se (

src/verilog/cpu/execute.sv

@@ -12,16 +12,18 @@ module alu (
   always_comb begin
     unique case (alu_control_i)
       // add
-      2'b00: result = a + b;
+      2'b00: result = a_i + b_i;
       // sub
-      2'b01: result = a - b;
+      2'b01: result = a_i - b_i;
       // sll
-      2'b10: result = a << b;
+      // can only shift by 32 pos
+      2'b10: result = a_i << b_i[4:0];
       // srl
-      2'b11: result = a >> b;
+      // can only shift by 32 pos
+      2'b11: result = a_i >> b_i[4:0];
     endcase
 
-    assign alu_zero_o = (result == 1'b0);
+    alu_zero_o = (result == 1'b0);
   end
 endmodule
 
@@ -39,8 +41,8 @@ module execute (
     output logic [31:0] pc_target_o
 );
 
-  logic [31:0] a = rs1_data;
+  logic [31:0] a = rs1_data_i;
-  logic [31:0] b = alu_src_i ? imm_ext_i : rs2_data;
+  logic [31:0] b = alu_src_i ? imm_ext_i : rs2_data_i;
 
   assign pc_target_o = current_pc_i + imm_ext_i;
 

src/verilog/cpu/sign_extend.sv

@@ -7,10 +7,12 @@ module sign_extend (
 );
 
   always_comb begin
+    imm_ext_o = '0;
+    instr_invld_o = 1'b0;
     case (imm_src_i)
       2'b00:   imm_ext_o = {{20{instr_i[31]}}, instr_i[31:20]};
-      2'b01:   imm_ext_o = {{20{instr_i[31]}}, instr_i[31:25], instr[11:7]};
+      2'b01:   imm_ext_o = {{20{instr_i[31]}}, instr_i[31:25], instr_i[11:7]};
-      2'b10:   imm_ext_o = {{20{instr_i[31]}}, instr_i[7], instr[30:25], instr_i[11:8], 1'b0};
+      2'b10:   imm_ext_o = {{20{instr_i[31]}}, instr_i[7], instr_i[30:25], instr_i[11:8], 1'b0};
       default: instr_invld_o = 1'b1;
     endcase
   end