init commit
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../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
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../../src/verilog/cpu/cpu_pkg.sv
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../../src/verilog/memory_controller.sv
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../../src/verilog/sram_wrapper.sv
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../../src/verilog/cpu/reg_file.sv
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../../src/verilog/cpu/fetch.sv
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../../src/verilog/cpu/cpu_top.sv
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../../src/verilog/chip_top.sv
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../../src/verilog/tb_processor.sv
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// you MUST add any new files you make to this include file, follow the path naming above
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// aka '../../src/verilog/cpu/(your module here).sv'
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// Add additional testbench(es) using this format
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// ../../src/verilog/tb_name_of_test.sv
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// Warning: If your added testbench create a text file,
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// please make sure it is commented out when you run verify_onboarding
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// as 2 testbench cannot write to text files at the same time
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@@ -0,0 +1,2 @@
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../../src/verilog/cpu/fetch.sv
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../../src/verilog/tb_fetch.sv
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@@ -0,0 +1,2 @@
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../../tests/mock/chip_top_mock.sv
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../../src/verilog/tb_processor.sv
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@@ -0,0 +1,101 @@
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#--------------------------------------------------------------------
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# Cadence‑only Makefile (Xcelium / SimVision / IMC)
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#--------------------------------------------------------------------
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#--------------------------------------------------------------------
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# Add the following to the testbench
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# initial begin
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# $shm_open("waves.shm");
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# $shm_probe("AC");
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# end
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#--------------------------------------------------------------------
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# ===== User‑configurable variables =================================
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INCLUDE_FILE_NAME ?= cpu.include #this is a placeholder
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TOP ?= tb_processor
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# ===== Paths =======================================================
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CURRENT_DIR := $(shell pwd)
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WORKSPACE := $(CURRENT_DIR)/WORKSPACE
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SCRIPT_DIR := ../../scripts
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PYTHON ?= python3
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# ===== Dynamic macro definitions ===================================
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VERILOG_DEFINES := SIM=1 INST_FILE=\"$(INST_FILE)\"
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ifeq ($(INIT_DATA),1)
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VERILOG_DEFINES += INIT_DATA=1
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VERILOG_DEFINES += DATA_FILE=\"$(DATA_FILE)\"
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endif
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DEFINE_FLAGS := $(foreach def,$(VERILOG_DEFINES),+define+$(def))
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# ===== Help Message ================================================
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.PHONY: help
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help:
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@echo "----------------------------------------------------------------"
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@echo "Administrative targets:"
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@echo " help - this message"
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@echo " clean - remove WORKSPACE directory"
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@echo
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@echo "Compilation targets:"
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@echo " link - generate WORKSPACE/sym_links/"
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@echo " xrun - compile & simulate using Cadence Xcelium"
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@echo " simvision - view waveform database"
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@echo " run_and_view - xrun + simvision"
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@echo " coverage - open coverage in IMC"
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@echo
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@echo " verify_onboarding - (DIGITAL DESIGN ONBOARDING ONLY) check your project for correctness"
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@echo "----------------------------------------------------------------"
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# ===== Administrative Targets ======================================
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.PHONY: clean link
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clean:
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@rm -rf $(WORKSPACE)
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link:
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@mkdir -p $(WORKSPACE)/sym_links
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@rm -rf $(WORKSPACE)/sym_links/*
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@$(PYTHON) link_files.py $(INCLUDE_FILE_NAME)
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# ===== Simulation Targets ==========================================
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.PHONY: xrun simvision run_and_view coverage
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XRUN_FLAGS = -64bit -sv -linedebug -access +rwc \
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-timescale 1ns/10ps \
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$(DEFINE_FLAGS) \
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+testname=$(TESTNAME) \
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+incdir+sym_links \
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-coverage all \
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-licqueue \
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-covoverwrite
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SIM_PLUSARGS ?=
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xrun: link
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cd $(WORKSPACE) && \
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xrun $(XRUN_FLAGS) -f sym_links/sim_no_path.include \
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-top $(TOP) -logfile simulation.log $(SIM_PLUSARGS)
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simvision:
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cd $(WORKSPACE) && simvision waves.shm &
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run_and_view: xrun simvision
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# Need to change IMC path...
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coverage:
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cd $(WORKSPACE) && /tools/software/cadence/vmanager/latest/tools.lnx86/vmgr/bin/imc -load cov_work/scope/test &
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# Generate memory pre and post state files but do not verify correctness
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gen_mem:
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$(MAKE) clean
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$(PYTHON) $(SCRIPT_DIR)/init_mem.py $(WORKSPACE)
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$(MAKE) xrun
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verify_onboarding:
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$(MAKE) clean
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$(PYTHON) $(SCRIPT_DIR)/init_mem.py $(WORKSPACE)
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$(MAKE) xrun
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$(PYTHON) $(SCRIPT_DIR)/check_onboarding.py $(WORKSPACE)/memory_post_state_lower.txt $(WORKSPACE)/sim_memory_post_state_lower.txt
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$(PYTHON) $(SCRIPT_DIR)/check_onboarding.py $(WORKSPACE)/memory_post_state_upper.txt $(WORKSPACE)/sim_memory_post_state_upper.txt
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# ===== Default Target ==============================================
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.DEFAULT_GOAL := run_and_view
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@@ -0,0 +1,57 @@
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import os
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import re
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import sys
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if len(sys.argv) != 2:
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print("Usage: python3 link_files.py <include_file_location>")
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sys.exit(1)
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# Input and output file names
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input_file = "Include/" + sys.argv[1]
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print("looking in file " + input_file)
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# Ensure WORKSPACE and sym_links directories exist
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workspace_dir = "WORKSPACE"
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sym_links_dir = os.path.join(workspace_dir, "sym_links")
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os.makedirs(sym_links_dir, exist_ok=True)
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# Output file path in WORKSPACE
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output_file = os.path.join(sym_links_dir, "sim_no_path.include")
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# Open input file for reading
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with open(input_file, 'r') as input_fp:
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# Open output file for writing
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with open(output_file, 'w') as output_fp:
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# Iterate through each line in the input file
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for line in input_fp:
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# Remove leading and trailing whitespaces
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line = line.strip()
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# Check if the line is a comment or empty
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if not line or line.startswith('//'):
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# If it's a comment or empty line, write it directly to the output file
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output_fp.write(line + '\n')
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else:
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# Extract the file path using regex
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match = re.match(r'^\s*(\S+)\s*$', line)
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if match:
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file_path = match.group(1)
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# Check if the file exists
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if os.path.exists(file_path):
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# Create symbolic link in WORKSPACE
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link_path = os.path.join(sym_links_dir, os.path.basename(file_path))
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try:
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os.symlink(os.path.abspath(file_path), link_path)
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except FileExistsError as e:
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print("Tried to symlink an already existing file: \n", e)
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print("Continuing")
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# Write only the filename to the output file
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output_fp.write(f"sym_links/{os.path.basename(file_path)}\n")
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else:
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print(f"Error: File '{file_path}' does not exist. Aborting process.")
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break
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else:
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print(f"Error: Invalid file path format in line '{line}'. Aborting process.")
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break
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