init commit

sim/behav/Include/cpu.include

@@ -0,0 +1,19 @@
+../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
+../../src/verilog/cpu/cpu_pkg.sv
+../../src/verilog/memory_controller.sv
+../../src/verilog/sram_wrapper.sv
+../../src/verilog/cpu/reg_file.sv
+../../src/verilog/cpu/fetch.sv
+
+../../src/verilog/cpu/cpu_top.sv
+../../src/verilog/chip_top.sv
+../../src/verilog/tb_processor.sv
+
+// you MUST add any new files you make to this include file, follow the path naming above
+// aka '../../src/verilog/cpu/(your module here).sv'
+
+// Add additional testbench(es) using this format
+// ../../src/verilog/tb_name_of_test.sv
+// Warning: If your added testbench create a text file, 
+// please make sure it is commented out when you run verify_onboarding
+// as 2 testbench cannot write to text files at the same time