From de40efad521afe158322fe622b8d817dfc849cfc Mon Sep 17 00:00:00 2001
From: dylanbenzi <dylanbenzi@gmail.com>
Date: Sun, 20 Sep 2026 16:12:44 -0400
Subject: [PATCH] update behav includes

---
 sim/behav/Include/cpu.include | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sim/behav/Include/cpu.include b/sim/behav/Include/cpu.include
index 05d4f8d..2b45226 100644
--- a/sim/behav/Include/cpu.include
+++ b/sim/behav/Include/cpu.include
@@ -8,6 +8,10 @@
 ../../src/verilog/cpu/cpu_top.sv
 ../../src/verilog/chip_top.sv
 ../../src/verilog/tb_processor.sv
+../../src/verilog/cpu/control_unit.sv
+../../src/verilog/cpu/decode.sv
+../../src/verilog/cpu/execute.sv
+../../src/verilog/cpu/sign_extend.sv
 
 // you MUST add any new files you make to this include file, follow the path naming above
 // aka '../../src/verilog/cpu/(your module here).sv'