instructions needed (R, I, S, B) ops needed: NOP (I) opcode: 001 0011, funct3: 000 note: same encoding as addi x0, x0, 0 ADD (R) opcode: 011 0011, funct3: 000, funct7: 000 0000 SUB (R) opcode: 011 0011, funct3: 000, funct7: 010 0000 SLL (R) opcode: 011 0011, funct3: 001, funct7: 000 0000 SRL (R) opcode: 011 0011, funct3: 101, funct7: 000 0000 ADDI (I) opcode: 001 0011, funct3: 000 LOAD (I) opcode: 000 0011, funct3: 010 STORE (S) opcode: 010 0011, funct3: 010 BEQ (B) opcode: 110 0011, funct3: 000 EBREAK (I) opcode: 111 0011, funct3: 000 - opcode [6:0] - funct3 [14:12] - rs1 [19:15] R type - opcode: 011 0011 - funct7 [31:25] - rs2 [24:20] - rs1 [19:15] - funct3 [14:12] - rd [11:7] - opcode [6:0] I type - opcode: 001 0011 | 000 0011 - imm [31:20] - rs1 [19:15] - funct3 [14:12] - rd [11:7] - opcode [6:0] S type - opcode: 010 0011 - imm [31:25] - rs2 [24:20] - rs1 [19:15] - funct3 [14:12] - imm [11:7] - opcode [6:0] B type - opcode: 110 0011 - imm [31:25] - rs2 [24:20] - rs1 [19:15] - funct3 [14:12] - imm [11:7] - opcode [6:0] main decoder truth table instr opcode regwrite immsrc alusrc memwrite resultsrc branch aluop add 0110011 1 xx 0 0 0 0 10 sub 0110011 1 xx 0 0 0 0 10 sll 0110011 1 xx 0 0 0 0 10 srl 0110011 1 xx 0 0 0 0 10 addi 0010011 1 00 1 0 0 0 10 lw 0000011 1 00 1 0 1 0 00 sw 0100011 0 01 1 1 x 0 00 beq 1100011 0 10 0 0 x 1 01 ebreak 1110011 x xx 0 0 0 1 01 alu decoder truth table aluop funct3 {op[5], funct7[5]} alucontrol instruction 00 x x 00 (add) lw, sw 01 x x 01 (sub) beq 10 000 00, 01, 10 00 (add) add, addi 000 11 01 (sub) sub 001 x 10 (sll) sll 101 x 11 (srl) srl