60 lines
1.2 KiB
Systemverilog
60 lines
1.2 KiB
Systemverilog
module alu (
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input logic [31:0] a_i,
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input logic [31:0] b_i,
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input logic [ 1:0] alu_control_i,
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output logic alu_zero_o,
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output logic [31:0] alu_result_o
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);
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logic [31:0] result;
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always_comb begin
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unique case (alu_control_i)
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// add
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2'b00: result = a_i + b_i;
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// sub
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2'b01: result = a_i - b_i;
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// sll
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// can only shift by 32 pos
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2'b10: result = a_i << b_i[4:0];
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// srl
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// can only shift by 32 pos
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2'b11: result = a_i >> b_i[4:0];
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endcase
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alu_zero_o = (result == 1'b0);
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end
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endmodule
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module execute (
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input logic clk_i,
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input logic alu_src_i,
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input logic [31:0] imm_ext_i,
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input logic [1:0] alu_control_i,
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input logic [31:0] current_pc_i,
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input logic [31:0] rs1_data_i,
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input logic [31:0] rs2_data_i,
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output logic alu_zero_o,
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output logic [31:0] alu_result_o,
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output logic [31:0] pc_target_o
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);
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logic [31:0] a;
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logic [31:0] b;
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assign a = rs1_data_i;
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assign b = alu_src_i ? imm_ext_i : rs2_data_i;
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assign pc_target_o = current_pc_i + imm_ext_i;
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alu alu (
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.a_i(a),
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.b_i(b),
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.alu_control_i(alu_control_i),
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.alu_zero_o(alu_zero_o),
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.alu_result_o(alu_result_o)
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);
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endmodule
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