66 lines
1.7 KiB
Systemverilog
66 lines
1.7 KiB
Systemverilog
module decode (
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input logic clk_i,
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input logic rst_i,
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input logic [31:0] instr_i, // instruction to decode
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input logic instr_vld_i, // is instruction passed valid
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input logic alu_zero_i,
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input logic [31:0] rd_data_i,
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output logic pc_src_o,
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output logic result_src_o,
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output logic mem_write_o,
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output logic alu_src_o,
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output logic [1:0] alu_control_o,
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output logic [31:0] imm_ext_o,
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output logic [31:0] rs1_data_o,
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output logic [31:0] rs2_data_o,
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output logic load_stall_o,
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output logic instr_invld_o,
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output logic ebreak_o,
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output logic [31:0] reg_values_o[32] //Register Values Output
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);
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logic [1:0] imm_src;
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logic reg_write;
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logic cu_invld;
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logic se_invld;
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assign instr_invld_o = ~instr_vld_i | cu_invld | se_invld; // instruction is invalid if provided invalid or decoded invalid
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control_unit cu (
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.instr_i(instr_i),
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.zero_flag_i(alu_zero_i),
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.pc_src_o(pc_src_o),
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.result_src_o(result_src_o),
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.mem_write_o(mem_write_o),
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.alu_src_o(alu_src_o),
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.imm_src_o(imm_src),
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.reg_write_o(reg_write),
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.alu_control_o(alu_control_o),
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.load_stall_o(load_stall_o),
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.instr_invld_o(cu_invld),
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.ebreak_o(ebreak_o)
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);
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reg_file rf (
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.clk_i(clk_i),
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.rst_i(rst_i),
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.rs1_addr_i(instr_i[19:15]),
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.rs2_addr_i(instr_i[24:20]),
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.rs1_data_o(rs1_data_o),
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.rs2_data_o(rs2_data_o),
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.rd_write_en_i(reg_write),
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.rd_addr_i(instr_i[11:7]),
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.rd_data_i(rd_data_i),
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.reg_values_o(reg_values_o)
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);
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sign_extend se (
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.instr_i(instr_i),
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.imm_src_i(imm_src),
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.imm_ext_o(imm_ext_o),
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.instr_invld_o(se_invld)
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);
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endmodule
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