46 lines
1.4 KiB
Systemverilog
46 lines
1.4 KiB
Systemverilog
// 32 x 32-bit RISC-V integer register file.
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// Register x0 always reads as zero and ignores writes.
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module reg_file (
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input logic clk_i,
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input logic rst_i,
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input logic [ 4:0] rs1_addr_i, //Register Source 1 Address Input
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input logic [ 4:0] rs2_addr_i,
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output logic [31:0] rs1_data_o,
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output logic [31:0] rs2_data_o, //Register Source 2 Data Output
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input logic rd_write_en_i, //Register Destination Write Enable Input
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input logic [ 4:0] rd_addr_i,
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input logic [31:0] rd_data_i,
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// Read-only architectural state exposed to the debug crossbar.
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output logic [31:0] reg_values_o[32] //Register Values Output
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);
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logic [31:0] registers[32];
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integer i; //used for generate loops in systemverilog
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always_comb begin
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rs1_data_o = (rs1_addr_i == 5'd0) ? 32'd0 : registers[rs1_addr_i];
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rs2_data_o = (rs2_addr_i == 5'd0) ? 32'd0 : registers[rs2_addr_i];
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end
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assign reg_values_o[0] = 32'd0;
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generate
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for (
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genvar register_index = 1; register_index < 32; register_index++
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) begin : gen_debug_register_values
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assign reg_values_o[register_index] = registers[register_index];
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end
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endgenerate
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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for (i = 0; i < 32; i = i + 1) registers[i] <= 32'd0;
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end else if (rd_write_en_i && (rd_addr_i != 5'd0)) begin
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registers[rd_addr_i] <= rd_data_i;
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end
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end
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endmodule
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