20 lines
742 B
Plaintext
20 lines
742 B
Plaintext
../../src/verilog/CF_SRAM_1024x32.tt_180V_25C.v
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../../src/verilog/cpu/cpu_pkg.sv
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../../src/verilog/memory_controller.sv
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../../src/verilog/sram_wrapper.sv
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../../src/verilog/cpu/reg_file.sv
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../../src/verilog/cpu/fetch.sv
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../../src/verilog/cpu/cpu_top.sv
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../../src/verilog/chip_top.sv
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../../src/verilog/tb_processor.sv
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// you MUST add any new files you make to this include file, follow the path naming above
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// aka '../../src/verilog/cpu/(your module here).sv'
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// Add additional testbench(es) using this format
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// ../../src/verilog/tb_name_of_test.sv
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// Warning: If your added testbench create a text file,
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// please make sure it is commented out when you run verify_onboarding
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// as 2 testbench cannot write to text files at the same time
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