62 lines
1.4 KiB
Systemverilog
62 lines
1.4 KiB
Systemverilog
//DO NOT MODIFY THIS FILE!
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//DO NOT MODIFY THIS FILE!!
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module fetch (
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input logic clk_i,
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input logic rst_i,
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input logic en_i,
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input logic stall_core_i,
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// === Instruction RAM Interface === //
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output logic isram_en_o,
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output logic [9:0] isram_addr_o,
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input logic [31:0] isram_rdata_i,
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input logic isram_rready_i,
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// === Fetched Instruction === //
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output logic [31:0] instr_o,
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output logic [31:0] pc_o, //current instruction
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output logic instr_vld_o,
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input logic branch_vld_i,
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input logic [9:0] branch_trgt_i,
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input logic branch_taken_i
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);
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logic [31:0] next_pc; //instruction to be run at the next cycle
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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pc_o <= '0;
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end else if (en_i & !stall_core_i) begin
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pc_o <= next_pc;
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end
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end
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always_comb begin
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next_pc = '0;
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isram_en_o = '0;
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isram_addr_o = '0;
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instr_o = '0;
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instr_vld_o = '0;
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if (en_i) begin
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if (stall_core_i) begin
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next_pc = pc_o; //when we stall we stay at the same instruction at the next cycle
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end else if (branch_vld_i && branch_taken_i) begin
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next_pc = {20'b0, branch_trgt_i, 2'b00};
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end else begin
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next_pc = pc_o + 4;
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end
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isram_en_o = 1'b1;
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isram_addr_o = next_pc[11:2];
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instr_o = isram_rdata_i;
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instr_vld_o = isram_rready_i;
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end
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end
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endmodule
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