add rtl files to sim include

2026-09-26 15:30:20 -04:00
parent 677b5a06b2
commit 5b15f9a019
1 changed files with 4 additions and 0 deletions
@@ -9,6 +9,10 @@
 ../../src/verilog/cpu/reg_file.sv
 ../../src/verilog/cpu/fetch.sv
 ../../src/verilog/cpu/cpu_top.sv
+../../src/verilog/cpu/control_unit.sv
+../../src/verilog/cpu/decode.sv
+../../src/verilog/cpu/execute.sv
+../../src/verilog/cpu/sign_extend.sv

 // Member testbench
 ../../src/verilog/tb/cpu_if.sv