add rtl files to sim include

sim/behav/Include/member.include

@@ -9,6 +9,10 @@
 ../../src/verilog/cpu/reg_file.sv
 ../../src/verilog/cpu/fetch.sv
 ../../src/verilog/cpu/cpu_top.sv
+../../src/verilog/cpu/control_unit.sv
+../../src/verilog/cpu/decode.sv
+../../src/verilog/cpu/execute.sv
+../../src/verilog/cpu/sign_extend.sv
 
 // Member testbench
 ../../src/verilog/tb/cpu_if.sv