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cpu_sb.svh todo comment fix

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Luo, Kevin
2026-09-23 11:15:40 -04:00
committed by GitHub Enterprise
parent f1ffe1e781
commit ec969afb47
1 changed files with 3 additions and 3 deletions
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src/verilog/tb/cpu_sb.svh
+3 -3
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@@ -148,7 +148,7 @@ class cpu_sb #(int DataSize=32, int AddrSize=14);
// TODO: Load both expected memories through the reference-model // TODO: Load both expected memories through the reference-model
// API and run it with MAX_REF_INSTR as its bound. Save predicted // API and run it with MAX_REF_INSTR as its bound. Save predicted
// registers and the ordered store queue, reset per-program counters, // registers and the ordered store queue, reset per-program counters,
// mark the program active, and sample the executed instruction trace. // and mark the program active.
fail("CPU_START prediction is not implemented"); fail("CPU_START prediction is not implemented");
end end
@@ -180,8 +180,8 @@ class cpu_sb #(int DataSize=32, int AddrSize=14);
// A normal halt must finish all expected CPU activity // A normal halt must finish all expected CPU activity
CPU_HALT: begin CPU_HALT: begin
// TODO: Check that every expected store was observed, compare // TODO: Check that every expected store was observed, compare
// final data memory with the reference model, sample program // final data memory with the reference model, and mark the
// coverage, and mark the program inactive. // program inactive.
fail("CPU_HALT checking is not implemented"); fail("CPU_HALT checking is not implemented");
end end