21 lines
551 B
Systemverilog
21 lines
551 B
Systemverilog
module sign_extend (
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input logic [31:0] instr_i,
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input logic [ 1:0] imm_src_i,
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output logic [31:0] imm_ext_o,
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output logic instr_invld_o
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);
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always_comb begin
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imm_ext_o = '0;
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instr_invld_o = 1'b0;
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case (imm_src_i)
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2'b00: imm_ext_o = {{20{instr_i[31]}}, instr_i[31:20]};
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2'b01: imm_ext_o = {{20{instr_i[31]}}, instr_i[31:25], instr_i[11:7]};
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2'b10: imm_ext_o = {{20{instr_i[31]}}, instr_i[7], instr_i[30:25], instr_i[11:8], 1'b0};
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default: instr_invld_o = 1'b1;
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endcase
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end
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endmodule
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