Merge remote-tracking branch 'upstream/main'

.gitignore

@@ -9,3 +9,8 @@ __pycache__/
 
 # Cadence/Xcelium simulation output
 sim/behav/WORKSPACE/
+
+# Submission packaging
+*-dd-fall26.zip
+regress.log
+submission.stamp

Makefile

@@ -1,3 +1,12 @@
+# Fill these in before running make submit, for example:
+#   MEMBER_NAME  = George Burdell
+#   GT_USERNAME  = gburdell3
+#   DISCORD_NAME = gburdell67discord
+MEMBER_NAME  =
+GT_USERNAME  =
+DISCORD_NAME =
+export MEMBER_NAME
+
 PYTHON ?= python3
 TEST ?= ebreak
 TEST_DIR := tests/$(TEST)
@@ -6,13 +15,14 @@ CROSSBAR_TIMEOUT ?= 20
 
 TEST_NAMES := $(sort $(notdir $(patsubst %/,%,$(dir $(wildcard tests/*/program.asm)))))
 
-.PHONY: help generate smoke test regress clean clean-generated
+.PHONY: help generate smoke test regress submit clean clean-generated
 
 help:
 	@echo "make generate TEST=<name>  Assemble a test and generate golden files"
 	@echo "make smoke                 Test build/TB wiring with a mock DUT"
 	@echo "make test TEST=<name>      Generate and run one RTL test"
 	@echo "make regress               Run every test, print PASS/FAIL summary (logs in tests/<name>/sim.log)"
+	@echo "make submit                Run regress and zip your sources, tests and log for checkoff"
 	@echo "make clean                 Remove generated test and simulator files"
 	@echo "Available tests: $(TEST_NAMES)"
 
@@ -54,6 +64,23 @@ regress:
 		exit 1; \
 	fi
 
+submit:
+	@if [ -z "$(strip $(MEMBER_NAME))" ] || [ -z "$(strip $(GT_USERNAME))" ] || [ -z "$(strip $(DISCORD_NAME))" ]; then \
+		echo "Fill in MEMBER_NAME, GT_USERNAME and DISCORD_NAME at the top of the Makefile first."; \
+		exit 2; \
+	fi
+	@submission="$$(printf '%s' "$$MEMBER_NAME" | tr -d "[:space:]'.,-")-$(strip $(GT_USERNAME))-$(strip $(DISCORD_NAME))-dd-fall26.zip"; \
+	rm -f "$$submission" regress.log submission.stamp; \
+	scripts/sjstamp submission.stamp regress.log src sim/behav/Include tests -- $(MAKE) --no-print-directory regress; \
+	status=$$?; \
+	if [ $$status -eq 125 ]; then echo "Could not stamp the submission, nothing was zipped."; exit 1; fi; \
+	zip -qr "$$submission" src sim/behav/Include tests regress.log submission.stamp \
+		-x '*.DS_Store' 'tests/*/program.o' 'tests/*/program.hex' 'tests/*/sim.log'; \
+	echo "----------------------------------------"; \
+	if [ $$status -ne 0 ]; then echo "WARNING: not all tests pass, see regress.log"; fi; \
+	echo "Wrote $$submission"
+
+>>>>>>> upstream/main
 clean:
 	$(MAKE) -C sim/behav clean
 	$(MAKE) --no-print-directory clean-generated

README.md

@@ -273,10 +273,12 @@ Disclaimer: We will be running some back end AI and software similarity checkers
 
 In Person Submissions: 
 - We will ask you to walk through the logic and answer a few random questions on must-know concepts. 
+- You still need to run `make submit` and send the zip to the sjcheckoffs Discord Account, same as an online submission. 
 
 Additional Instructions For Online Submissions: 
 - Include a screenshot of all your tests passing with your gt username somewhere in the terminal in the screenshot
-- **submit a zip of the src folder to the sjcheckoffs Discord Account​** <img width="417" height="422" alt="image" src="https://github.gatech.edu/user-attachments/assets/1c271294-ba6a-4314-beb2-e4c76c7e97db" />
+- fill in your name, GT username and Discord username at the top of the `Makefile`, then run `make submit` to run every test and build the zip
+- **submit the zip that `make submit` wrote to the sjcheckoffs Discord Account​** <img width="417" height="422" alt="image" src="https://github.gatech.edu/user-attachments/assets/1c271294-ba6a-4314-beb2-e4c76c7e97db" />
 - Include any supporting documentation you may have used (diagrams, drawings, state machines) 
 
 

src/verilog/cpu/cpu_top.sv

@@ -5,6 +5,7 @@
 // END SYSTEM HEADER
 
 module cpu_top (
+<<<<<<< HEAD
     input logic clk_i,
     input logic rst_i,
     input logic en_i,

src/verilog/cpu/fetch.sv

@@ -28,9 +28,9 @@ module fetch (
 	logic [31:0] next_pc; //instruction to be run at the next cycle
 	
 	always_ff @(posedge clk_i) begin
-    if (rst_i) begin
+		if(rst_i) begin
 			pc_o <= '0;
-    end else if (en_i & !stall_core_i) begin
+		end else if(en_i & !stall_core_i) begin
 			pc_o <= next_pc;
 		end
 	end
@@ -41,7 +41,7 @@ module fetch (
 		isram_addr_o	= '0;
 		instr_o 	= '0;
 		instr_vld_o	= '0;
-    if (en_i) begin
+		if(en_i) begin
 			if (stall_core_i) begin
 				next_pc = pc_o; //when we stall we stay at the same instruction at the next cycle
 			end else if (branch_vld_i && branch_taken_i) begin

src/verilog/cpu/reg_file.sv

@@ -4,20 +4,20 @@ module reg_file (
     input  logic        clk_i,
     input  logic        rst_i,
 
-    input  logic [ 4:0] rs1_addr_i,  //Register Source 1 Address Input
-    input  logic [ 4:0] rs2_addr_i,
+    input  logic [4:0]  rs1_addr_i, //Register Source 1 Address Input
+    input  logic [4:0]  rs2_addr_i,
     output logic [31:0] rs1_data_o,
     output logic [31:0] rs2_data_o, //Register Source 2 Data Output
 
     input  logic        rd_write_en_i, //Register Destination Write Enable Input
-    input logic [ 4:0] rd_addr_i,
+    input  logic [4:0]  rd_addr_i,
     input  logic [31:0] rd_data_i,
 
     // Read-only architectural state exposed to the debug crossbar.
-    output logic [31:0] reg_values_o[32]  //Register Values Output
+    output logic [31:0] reg_values_o [0:31] //Register Values Output
 );
 
-  logic [31:0] registers[32];
+    logic [31:0] registers [0:31];
     integer i; //used for generate loops in systemverilog
 
     always_comb begin
@@ -27,16 +27,17 @@ module reg_file (
 
     assign reg_values_o[0] = 32'd0;
     generate
-    for (
-        genvar register_index = 1; register_index < 32; register_index++
-    ) begin : gen_debug_register_values
+        for (genvar register_index = 1;
+             register_index < 32;
+             register_index++) begin : gen_debug_register_values
             assign reg_values_o[register_index] = registers[register_index];
         end
     endgenerate
 
     always_ff @(posedge clk_i) begin
         if (rst_i) begin
-      for (i = 0; i < 32; i = i + 1) registers[i] <= 32'd0;
+            for (i = 0; i < 32; i = i + 1)
+                registers[i] <= 32'd0;
         end else if (rd_write_en_i && (rd_addr_i != 5'd0)) begin
             registers[rd_addr_i] <= rd_data_i;
         end

src/verilog/sram_wrapper.sv

@@ -7,7 +7,7 @@ module sram_wrapper (
     input  logic        rst_i,	
     input  logic        en_i,
     input  logic        write_en_i,
-    input  logic [ 9:0] addr_i,
+    input  logic [9:0]  addr_i,
     input  logic [31:0] wdata_i,
     output logic [31:0] rdata_o,
     output logic 	rready_o
@@ -28,7 +28,7 @@ module sram_wrapper (
     	    .ScanInCC  (1'b0),
     	    .ScanInDL  (1'b0),
     	    .ScanInDR  (1'b0),
-      .ScanOutCC(),
+    	    .ScanOutCC (),
     	    .vpwrac    (1'b1),
     	    .vpwrpc    (1'b1)
     	);
@@ -37,7 +37,7 @@ module sram_wrapper (
 	logic rdata_valid;
 
 	always_ff @(posedge clk_i) begin
-    if (rst_i) begin
+		if(rst_i) begin
 			rdata_valid <= 1'b0;
 		end else begin
 			rdata_valid <= en_i;