fix load stall logic

src/verilog/cpu/cpu_top.sv

@@ -60,14 +60,22 @@ module cpu_top (
   logic ebreak_latch;
   logic load_stall;
   logic load_stall_cycle;
+  logic load_stall_ff;
 
-  assign stall_core = ebreak_latch | halted_o | ~en_i;
+  assign load_stall_ff = (load_stall & ~load_stall_cycle);
+
+  assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall_ff;
 
   always_ff @(posedge clk_i) begin
-    if (load_stall & ~load_stall_cycle) begin
-      stall_core <= 1'b1;
+    if (rst_i) begin
+      halted_o <= 1'b0;
       load_stall_cycle <= 1'b0;
-    end else if (load_stall & load_stall_cycle) stall_core <= 1'b0;
+    end else if (ebreak_latch) halted_o <= 1'b1;
+    else if (load_stall & ~load_stall_cycle) begin
+      load_stall_cycle <= 1'b1;
+    end else if (load_stall & load_stall_cycle) begin
+      load_stall_cycle <= 1'b0;
+    end
   end
 
   // === Instruction Fetch === //
@@ -109,17 +117,12 @@ module cpu_top (
       .rs1_data_o(rs1_data),
       .rs2_data_o(rs2_data),
       .load_stall_o(load_stall),
+      .load_stall_ff_i(load_stall_ff),
       .instr_invld_o(instr_invld_decode),
       .reg_values_o(reg_crossbar_o),
       .ebreak_o(ebreak_latch)
   );
 
-  always_ff @(posedge clk_i) begin
-    if (rst_i) halted_o <= 1'b0;
-    else if (ebreak_latch) halted_o <= 1'b1;
-  end
-
-
   always_comb begin
     if (pc_target[31:12] == '0) begin
       branch_vld  = '1;

src/verilog/cpu/decode.sv

@@ -5,6 +5,7 @@ module decode (
     input logic instr_vld_i,  // is instruction passed valid
     input logic alu_zero_i,
     input logic [31:0] rd_data_i,
+    input logic load_stall_ff_i,
 
     output logic pc_src_o,
     output logic result_src_o,
@@ -49,7 +50,7 @@ module decode (
       .rs2_addr_i(instr_i[24:20]),
       .rs1_data_o(rs1_data_o),
       .rs2_data_o(rs2_data_o),
-      .rd_write_en_i(reg_write),
+      .rd_write_en_i(reg_write & ~load_stall_ff_i),
       .rd_addr_i(instr_i[11:7]),
       .rd_data_i(rd_data_i),
       .reg_values_o(reg_values_o)