update load stall condition

src/verilog/cpu/cpu_top.sv

@@ -59,8 +59,16 @@ module cpu_top (
 
   logic ebreak_latch;
   logic load_stall;
+  logic load_stall_cycle;
 
-  assign stall_core = ebreak_latch | halted_o | ~en_i | load_stall;  //when else would you stall?
+  assign stall_core = ebreak_latch | halted_o | ~en_i;
+
+  always_ff @(posedge clk_i) begin
+    if (load_stall & ~load_stall_cycle) begin
+      stall_core <= 1'b1;
+      load_stall_cycle <= 1'b0;
+    end else if (load_stall & load_stall_cycle) stall_core <= 1'b0;
+  end
 
   // === Instruction Fetch === //
   // certain ports are tied off bc they depend on modulees you need to implement.