fix halt logic

src/verilog/cpu/cpu_top.sv

@@ -56,7 +56,9 @@ module cpu_top (
 
   logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
 
-  assign stall_core = halted_o | ~en_i;  //when else would you stall?
+  logic ebreak_latch;
+
+  assign stall_core = ebreak_latch | halted_o | ~en_i;  //when else would you stall?
 
   // === Instruction Fetch === //
   // certain ports are tied off bc they depend on modulees you need to implement.
@@ -98,9 +100,14 @@ module cpu_top (
       .rs2_data_o(rs2_data),
       .instr_invld_o(instr_invld_decode),
       .reg_values_o(reg_crossbar_o),
-      .ebreak_o(halted_o)
+      .ebreak_o(ebreak_latch)
   );
 
+  always_ff @(posedge clk_i) begin
+    if (rst_i) halted_o <= 1'b0;
+    else if (ebreak_latch) halted_o <= 1'b1;
+  end
+
 
   always_comb begin
     if (pc_target[31:12] == '0) begin