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fix load stall declaration

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dylan
2026-09-20 18:33:39 -04:00
parent 9eb9bde62f
commit 5856ab3d7c
1 changed files with 2 additions and 2 deletions
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src/verilog/cpu/control_unit.sv
+2 -2
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@@ -21,7 +21,7 @@ module main_decoder (
mem_write_o = 1'b0; mem_write_o = 1'b0;
alu_src_o = 1'b0; alu_src_o = 1'b0;
alu_op_o = 1'b00; alu_op_o = 1'b00;
load_stall = 1'b0; load_stall_o = 1'b0;
case (opcode_i) case (opcode_i)
// lw // lw
@@ -33,7 +33,7 @@ module main_decoder (
result_src_o = 1'b1; result_src_o = 1'b1;
branch_o = 1'b0; branch_o = 1'b0;
alu_op_o = 2'b00; alu_op_o = 2'b00;
load_stall = 1'b1; load_stall_o = 1'b1;
end end
// sw // sw
7'b0100011: begin 7'b0100011: begin