fix load stall declaration

src/verilog/cpu/control_unit.sv

@@ -21,7 +21,7 @@ module main_decoder (
     mem_write_o = 1'b0;
     alu_src_o = 1'b0;
     alu_op_o = 1'b00;
-    load_stall = 1'b0;
+    load_stall_o = 1'b0;
 
     case (opcode_i)
       // lw
@@ -33,7 +33,7 @@ module main_decoder (
         result_src_o = 1'b1;
         branch_o = 1'b0;
         alu_op_o = 2'b00;
-        load_stall = 1'b1;
+        load_stall_o = 1'b1;
       end
       // sw
       7'b0100011: begin