fix logic assign bugs

src/verilog/cpu/cpu_top.sv

@@ -54,7 +54,8 @@ module cpu_top (
   logic [9:0] branch_trgt;
   logic branch_taken;
 
-  logic [31:0] result = result_src ? dsram_rdata_i : alu_result;
+  logic [31:0] result;
+  assign result = result_src ? dsram_rdata_i : alu_result;
 
   logic ebreak_latch;